Rangeanalysis: Remove superfluous ignoreZeroLowerBound.

This commit is contained in:
Anders Schack-Mulligen
2023-11-01 11:51:46 +01:00
parent 34b9791e46
commit 48291dd32d
4 changed files with 1 additions and 29 deletions

View File

@@ -16,14 +16,6 @@ module CppLangImplConstant implements LangSig<Sem, FloatDelta> {
*/
predicate ignoreExprBound(SemExpr e) { none() }
/**
* Ignore any inferred zero lower bound on this expression.
*
* This predicate is to keep the results identical to the original Java implementation. It should be
* removed once we have the new implementation matching the old results exactly.
*/
predicate ignoreZeroLowerBound(SemExpr e) { none() }
/**
* Holds if `e >= bound` (if `upper = false`) or `e <= bound` (if `upper = true`).
*/

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@@ -48,14 +48,6 @@ module CppLangImplRelative implements LangSig<Sem, FloatDelta> {
t instanceof SemFloatingPointType and lb = -(1.0 / 0.0) and ub = 1.0 / 0.0
}
/**
* Ignore any inferred zero lower bound on this expression.
*
* This predicate is to keep the results identical to the original Java implementation. It should be
* removed once we have the new implementation matching the old results exactly.
*/
predicate ignoreZeroLowerBound(SemExpr e) { none() }
/**
* Holds if `e >= bound` (if `upper = false`) or `e <= bound` (if `upper = true`).
*/

View File

@@ -373,8 +373,6 @@ module JavaLangImpl implements LangSig<Sem, IntDelta> {
predicate ignoreExprBound(Sem::Expr e) { none() }
predicate ignoreZeroLowerBound(Sem::Expr e) { none() }
predicate additionalValueFlowStep(Sem::Expr dest, Sem::Expr src, int delta) { none() }
Sem::Type getAlternateType(Sem::Expr e) { none() }

View File

@@ -268,14 +268,6 @@ signature module LangSig<Semantic Sem, DeltaSig D> {
*/
predicate ignoreExprBound(Sem::Expr e);
/**
* Ignore any inferred zero lower bound on this expression.
*
* This predicate is to keep the results identical to the original Java implementation. It should be
* removed once we have the new implementation matching the old results exactly.
*/
predicate ignoreZeroLowerBound(Sem::Expr e);
/**
* Holds if the value of `dest` is known to be `src + delta`.
*/
@@ -1066,9 +1058,7 @@ module RangeStage<
or
upper = false and
b = D::fromInt(0) and
semPositive(e.(Sem::BitAndExpr).getAnOperand()) and
// REVIEW: We let the language opt out here to preserve original results.
not ignoreZeroLowerBound(e)
semPositive(e.(Sem::BitAndExpr).getAnOperand())
}
/**