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d39b0fd3f4
DIL before
```
/* AST::AstNode */ AST#87953007::Cached::TAstNode result) =
fastTC(AST#a6718388::AstNode::getAChild#0#dispred#ff/2)
.
Synthesis#d9ff06b1::isInDesugaredContext#1#f(/* AST::AstNode */ unique AST#87953007::Cached::TAstNode n)
:-
exists(int arg1, /* AST::AstNode */ dontcare AST#87953007::Cached::TAstNode _ |
arg1 = -1, AST#87953007::Cached::getSynthChild#2(_, arg1, n)
);
exists(/* AST::AstNode */ AST#87953007::Cached::TAstNode call_result#2 |
exists(int arg1,
/* AST::AstNode */ dontcare AST#87953007::Cached::TAstNode _ |
arg1 = -1, AST#87953007::Cached::getSynthChild#2(_, arg1, call_result#2)
),
#AST#a6718388::AstNode::getAChild#0#dispredPlus#ff(call_result#2, n)
)
.
```
DIL after
```
incremental
Synthesis#d9ff06b1::isInDesugaredContext#1#f(/* AST::AstNode */ unique AST#87953007::Cached::TAstNode n)
:-
exists(int arg1, /* AST::AstNode */ dontcare AST#87953007::Cached::TAstNode _ |
arg1 = -1, AST#87953007::Cached::getSynthChild#2(_, arg1, n)
);
exists(/* AST::AstNode */ AST#87953007::Cached::TAstNode any#expr##2 |
rec Synthesis#d9ff06b1::isInDesugaredContext#1#f(any#expr##2),
exists(cached dontcare string _ |
AST#a6718388::AstNode::getAChild#1#dispred(any#expr##2, _, n)
)
)
| [base_case]
exists(int arg1, /* AST::AstNode */ dontcare AST#87953007::Cached::TAstNode _ |
arg1 = -1, AST#87953007::Cached::getSynthChild#2(_, arg1, n)
)
| [delta_order]
exists(/* AST::AstNode */ AST#87953007::Cached::TAstNode any#expr##2 |
delta previous rec Synthesis#d9ff06b1::isInDesugaredContext#1#f(any#expr##2),
project#AST#a6718388::AstNode::getAChild#1#dispred(any#expr##2, n)
),
not(previous rec Synthesis#d9ff06b1::isInDesugaredContext#1#f(n))
.
``