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C++: Add a large QLDoc with example to 'getInstructionSuccessor'.
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@@ -511,7 +511,79 @@ private module Cached {
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* that node is its successor in the new successor relation, and the Chi node's successors are
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* that node is its successor in the new successor relation, and the Chi node's successors are
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* the new instructions generated from the successors of the old instruction.
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* the new instructions generated from the successors of the old instruction.
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*
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*
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* Furthermore, the entry block is augmented with `UninitializedGroup` instructions.
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* Furthermore, the entry block is augmented with `UninitializedGroup` instructions and `Chi`
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* instructions. For example, consider this example:
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* ```cpp
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* int x, y;
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* int* p;
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* if(b) {
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* p = &x;
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* escape(&x);
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* } else {
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* p = &y;
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* }
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* *p = 42;
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*
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* int z, w;
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* int* q;
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* if(b) {
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* q = &z;
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* } else {
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* q = &w;
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* }
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* *q = 43;
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* ```
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*
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* the unaliased IR for the entry block of this snippet is:
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* ```
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* v1(void) = EnterFunction :
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* m1(unknown) = AliasedDefinition :
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* m2(unknown) = InitializeNonLocal :
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* r1(glval<bool>) = VariableAddress[b] :
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* m3(bool) = InitializeParameter[b] : &:r1
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* r2(glval<int>) = VariableAddress[x] :
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* m4(int) = Uninitialized[x] : &:r2
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* r3(glval<int>) = VariableAddress[y] :
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* m5(int) = Uninitialized[y] : &:r3
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* r4(glval<int *>) = VariableAddress[p] :
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* m6(int *) = Uninitialized[p] : &:r4
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* r5(glval<bool>) = VariableAddress[b] :
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* r6(bool) = Load[b] : &:r5, m3
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* v2(void) = ConditionalBranch : r6
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* ```
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* and we need to transform this to aliased IR by inserting an `UninitializedGroup`
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* instruction for every `VariableGroup` memory location in the function. Furthermore,
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* if the `VariableGroup` memory location contains an allocation that escapes we need
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* to insert a `Chi` that writes the memory produced by `UninitializedGroup` into
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* `{AllAliasedMemory}`. For the above snippet we then end up with:
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* ```
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* v1(void) = EnterFunction :
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* m2(unknown) = AliasedDefinition :
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* m3(unknown) = InitializeNonLocal :
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* m4(unknown) = Chi : total:m2, partial:m3
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* m5(int) = UninitializedGroup[x,y] :
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* m6(unknown) = Chi : total:m4, partial:m5
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* m7(int) = UninitializedGroup[w,z] :
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* r1(glval<bool>) = VariableAddress[b] :
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* m8(bool) = InitializeParameter[b] : &:r1
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* r2(glval<int>) = VariableAddress[x] :
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* m10(int) = Uninitialized[x] : &:r2
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* m11(unknown) = Chi : total:m6, partial:m10
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* r3(glval<int>) = VariableAddress[y] :
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* m12(int) = Uninitialized[y] : &:r3
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* m13(unknown) = Chi : total:m11, partial:m12
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* r4(glval<int *>) = VariableAddress[p] :
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* m14(int *) = Uninitialized[p] : &:r4
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* r5(glval<bool>) = VariableAddress[b] :
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* r6(bool) = Load[b] : &:r5, m8
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* v2(void) = ConditionalBranch : r6
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* ```
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*
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* Here, the group `{x, y}` contains an allocation that escapes (`x`), so there
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* is a `Chi` after the `UninitializedGroup` that initializes the memory for the
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* `VariableGroup` containing `x`. None of the allocations in `{w, z}` escape so
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* there is no `Chi` following that the `UninitializedGroup` that initializes the
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* memory of `{w, z}`.
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*/
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*/
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cached
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cached
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Instruction getInstructionSuccessor(Instruction instruction, EdgeKind kind) {
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Instruction getInstructionSuccessor(Instruction instruction, EdgeKind kind) {
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