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https://github.com/github/codeql.git
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Merge pull request #9130 from jketema/cpp17-init
C++: Handle C++17 if and switch initializers
This commit is contained in:
Jeroen Ketema
@@ -0,0 +1,21 @@
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class Element extends @element {
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string toString() { none() }
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}
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class Expr extends @expr {
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string toString() { none() }
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}
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class Stmt extends @stmt {
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string toString() { none() }
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}
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predicate isStmtWithInitializer(Stmt stmt) {
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exists(int kind | stmts(stmt, kind, _) | kind = 2 or kind = 11 or kind = 35)
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}
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from Expr child, int index, int index_new, Element parent
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where
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exprparents(child, index, parent) and
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if isStmtWithInitializer(parent) then index_new = index - 1 else index_new = index
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select child, index_new, parent
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2111
cpp/downgrades/cf72c8898d19eb1b3374432cf79d8276cb07ad43/old.dbscheme
Normal file
2111
cpp/downgrades/cf72c8898d19eb1b3374432cf79d8276cb07ad43/old.dbscheme
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,22 @@
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class Element extends @element {
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string toString() { none() }
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}
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class Stmt extends @stmt {
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string toString() { none() }
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}
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predicate isStmtWithInitializer(Stmt stmt) {
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exists(int kind | stmts(stmt, kind, _) | kind = 2 or kind = 11 or kind = 35)
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}
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from Stmt child, int index, int index_new, Element parent
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where
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stmtparents(child, index, parent) and
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(
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not isStmtWithInitializer(parent)
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or
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index > 0
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) and
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if isStmtWithInitializer(parent) then index_new = index - 1 else index_new = index
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select child, index_new, parent
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@@ -0,0 +1,6 @@
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description: Support C++17 if and switch initializers
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compatibility: partial
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if_initialization.rel: delete
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switch_initialization.rel: delete
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exprparents.rel: run exprparents.qlo
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stmtparents.rel: run stmtparents.qlo
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@@ -0,0 +1,4 @@
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---
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category: feature
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---
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* A `getInitialization` predicate was added to the `ConstexprIfStmt`, `IfStmt`, and `SwitchStmt` classes that yields the C++17-style initializer of the `if` or `switch` statement when it exists.
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@@ -663,18 +663,24 @@ private predicate namedStmtChildPredicates(Locatable s, Element e, string pred)
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or
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s.(ComputedGotoStmt).getExpr() = e and pred = "getExpr()"
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or
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s.(ConstexprIfStmt).getInitialization() = e and pred = "getInitialization()"
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or
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s.(ConstexprIfStmt).getCondition() = e and pred = "getCondition()"
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or
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s.(ConstexprIfStmt).getThen() = e and pred = "getThen()"
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or
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s.(ConstexprIfStmt).getElse() = e and pred = "getElse()"
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or
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s.(IfStmt).getInitialization() = e and pred = "getInitialization()"
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or
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s.(IfStmt).getCondition() = e and pred = "getCondition()"
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or
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s.(IfStmt).getThen() = e and pred = "getThen()"
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or
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s.(IfStmt).getElse() = e and pred = "getElse()"
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or
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s.(SwitchStmt).getInitialization() = e and pred = "getInitialization()"
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or
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s.(SwitchStmt).getExpr() = e and pred = "getExpr()"
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or
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s.(SwitchStmt).getStmt() = e and pred = "getStmt()"
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@@ -708,30 +708,33 @@ private predicate straightLineSparse(Node scope, int i, Node ni, Spec spec) {
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or
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scope =
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any(SwitchStmt s |
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// SwitchStmt [-> init] -> expr
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i = -1 and ni = s and spec.isAt()
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or
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i = 0 and ni = s.getExpr() and spec.isAround()
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i = 0 and ni = s.getInitialization() and spec.isAround()
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or
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i = 1 and ni = s.getExpr() and spec.isAround()
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or
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// If the switch body is not a block then this step is skipped, and the
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// expression jumps directly to the cases.
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i = 1 and ni = s.getStmt().(BlockStmt) and spec.isAt()
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i = 2 and ni = s.getStmt().(BlockStmt) and spec.isAt()
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or
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i = 2 and ni = s.getASwitchCase() and spec.isBefore()
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i = 3 and ni = s.getASwitchCase() and spec.isBefore()
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or
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// If there is no default case, we can jump to after the block. Note: `i`
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// is same value as above.
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not s.getASwitchCase() instanceof DefaultCase and
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i = 2 and
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i = 3 and
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ni = s.getStmt() and
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spec.isAfter()
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or
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i = 3 and /* BARRIER */ ni = s and spec.isBarrier()
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i = 4 and /* BARRIER */ ni = s and spec.isBarrier()
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or
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i = 4 and ni = s.getStmt() and spec.isAfter()
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i = 5 and ni = s.getStmt() and spec.isAfter()
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or
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i = 5 and ni = s and spec.isAroundDestructors()
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i = 6 and ni = s and spec.isAroundDestructors()
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or
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i = 6 and ni = s and spec.isAfter()
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i = 7 and ni = s and spec.isAfter()
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)
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or
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scope =
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@@ -836,8 +839,15 @@ private predicate subEdge(Pos p1, Node n1, Node n2, Pos p2) {
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p2.nodeAt(n2, f)
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)
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or
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// IfStmt -> condition ; { then, else } ->
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// IfStmt -> [ init -> ] condition ; { then, else } ->
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exists(IfStmt s |
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p1.nodeAt(n1, s) and
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p2.nodeBefore(n2, s.getInitialization())
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or
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p1.nodeAfter(n1, s.getInitialization()) and
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p2.nodeBefore(n2, s.getCondition())
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or
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not exists(s.getInitialization()) and
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p1.nodeAt(n1, s) and
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p2.nodeBefore(n2, s.getCondition())
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or
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@@ -851,8 +861,15 @@ private predicate subEdge(Pos p1, Node n1, Node n2, Pos p2) {
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p2.nodeAfter(n2, s)
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)
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or
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// ConstexprIfStmt -> condition ; { then, else } -> // same as IfStmt
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// ConstexprIfStmt -> [ init -> ] condition ; { then, else } -> // same as IfStmt
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exists(ConstexprIfStmt s |
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p1.nodeAt(n1, s) and
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p2.nodeBefore(n2, s.getInitialization())
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or
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p1.nodeAfter(n1, s.getInitialization()) and
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p2.nodeBefore(n2, s.getCondition())
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or
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not exists(s.getInitialization()) and
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p1.nodeAt(n1, s) and
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p2.nodeBefore(n2, s.getCondition())
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or
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@@ -421,20 +421,36 @@ class TranslatedCatchAnyHandler extends TranslatedHandler {
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class TranslatedIfStmt extends TranslatedStmt, ConditionContext {
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override IfStmt stmt;
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override Instruction getFirstInstruction() { result = getCondition().getFirstInstruction() }
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override Instruction getFirstInstruction() {
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if hasInitialization()
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then result = getInitialization().getFirstInstruction()
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else result = getFirstConditionInstruction()
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}
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override TranslatedElement getChild(int id) {
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id = 0 and result = getCondition()
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id = 0 and result = getInitialization()
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or
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id = 1 and result = getThen()
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id = 1 and result = getCondition()
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or
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id = 2 and result = getElse()
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id = 2 and result = getThen()
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or
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id = 3 and result = getElse()
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}
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private predicate hasInitialization() { exists(stmt.getInitialization()) }
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private TranslatedStmt getInitialization() {
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result = getTranslatedStmt(stmt.getInitialization())
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}
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private TranslatedCondition getCondition() {
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result = getTranslatedCondition(stmt.getCondition().getFullyConverted())
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}
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private Instruction getFirstConditionInstruction() {
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result = getCondition().getFirstInstruction()
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}
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private TranslatedStmt getThen() { result = getTranslatedStmt(stmt.getThen()) }
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private TranslatedStmt getElse() { result = getTranslatedStmt(stmt.getElse()) }
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@@ -456,6 +472,9 @@ class TranslatedIfStmt extends TranslatedStmt, ConditionContext {
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}
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override Instruction getChildSuccessor(TranslatedElement child) {
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child = getInitialization() and
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result = getFirstConditionInstruction()
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or
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(child = getThen() or child = getElse()) and
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result = getParent().getChildSuccessor(this)
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}
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@@ -698,14 +717,28 @@ class TranslatedSwitchStmt extends TranslatedStmt {
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result = getTranslatedExpr(stmt.getExpr().getFullyConverted())
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}
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private Instruction getFirstExprInstruction() { result = getExpr().getFirstInstruction() }
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private TranslatedStmt getBody() { result = getTranslatedStmt(stmt.getStmt()) }
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override Instruction getFirstInstruction() { result = getExpr().getFirstInstruction() }
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override Instruction getFirstInstruction() {
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if hasInitialization()
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then result = getInitialization().getFirstInstruction()
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else result = getFirstExprInstruction()
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}
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override TranslatedElement getChild(int id) {
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id = 0 and result = getExpr()
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id = 0 and result = getInitialization()
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or
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id = 1 and result = getBody()
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id = 1 and result = getExpr()
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or
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id = 2 and result = getBody()
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}
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private predicate hasInitialization() { exists(stmt.getInitialization()) }
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private TranslatedStmt getInitialization() {
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result = getTranslatedStmt(stmt.getInitialization())
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}
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override predicate hasInstruction(Opcode opcode, InstructionTag tag, CppType resultType) {
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@@ -735,6 +768,8 @@ class TranslatedSwitchStmt extends TranslatedStmt {
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}
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override Instruction getChildSuccessor(TranslatedElement child) {
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child = getInitialization() and result = getFirstExprInstruction()
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or
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child = getExpr() and result = getInstruction(SwitchBranchTag())
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or
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child = getBody() and result = getParent().getChildSuccessor(this)
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@@ -213,6 +213,26 @@ class ConditionalStmt extends ControlStructure, TConditionalStmt { }
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class IfStmt extends ConditionalStmt, @stmt_if {
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override string getAPrimaryQlClass() { result = "IfStmt" }
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/**
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* Gets the initialization statement of this 'if' statement, if any.
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*
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* For example, for
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* ```
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* if (int x = y; b) { f(); }
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* ```
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* the result is `int x = y;`.
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*
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* Does not hold if the initialization statement is missing or an empty statement, as in
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* ```
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* if (b) { f(); }
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* ```
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* or
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* ```
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* if (; b) { f(); }
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* ```
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*/
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Stmt getInitialization() { if_initialization(underlyingElement(this), unresolveElement(result)) }
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/**
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* Gets the condition expression of this 'if' statement.
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*
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@@ -222,7 +242,7 @@ class IfStmt extends ConditionalStmt, @stmt_if {
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* ```
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* the result is `b`.
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*/
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Expr getCondition() { result = this.getChild(0) }
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Expr getCondition() { result = this.getChild(1) }
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override Expr getControllingExpr() { result = this.getCondition() }
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@@ -299,6 +319,28 @@ class IfStmt extends ConditionalStmt, @stmt_if {
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class ConstexprIfStmt extends ConditionalStmt, @stmt_constexpr_if {
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override string getAPrimaryQlClass() { result = "ConstexprIfStmt" }
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/**
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* Gets the initialization statement of this 'constexpr if' statement, if any.
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*
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* For example, for
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* ```
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* if constexpr (int x = y; b) { f(); }
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* ```
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* the result is `int x = y;`.
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*
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* Does not hold if the initialization statement is missing or an empty statement, as in
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* ```
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* if constexpr (b) { f(); }
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* ```
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* or
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* ```
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* if constexpr (; b) { f(); }
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* ```
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*/
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Stmt getInitialization() {
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constexpr_if_initialization(underlyingElement(this), unresolveElement(result))
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}
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/**
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* Gets the condition expression of this 'constexpr if' statement.
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*
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@@ -308,7 +350,7 @@ class ConstexprIfStmt extends ConditionalStmt, @stmt_constexpr_if {
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* ```
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* the result is `b`.
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*/
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Expr getCondition() { result = this.getChild(0) }
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Expr getCondition() { result = this.getChild(1) }
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override Expr getControllingExpr() { result = this.getCondition() }
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@@ -926,7 +968,7 @@ class ForStmt extends Loop, @stmt_for {
|
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*
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* Does not hold if the initialization statement is an empty statement, as in
|
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* ```
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* for (; i < 10; i++) { j++ }
|
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* for (; i < 10; i++) { j++; }
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* ```
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*/
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Stmt getInitialization() { for_initialization(underlyingElement(this), unresolveElement(result)) }
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@@ -1470,6 +1512,28 @@ class DefaultCase extends SwitchCase {
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class SwitchStmt extends ConditionalStmt, @stmt_switch {
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override string getAPrimaryQlClass() { result = "SwitchStmt" }
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|
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/**
|
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* Gets the initialization statement of this 'switch' statement, if any.
|
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*
|
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* For example, for
|
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* ```
|
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* switch (int x = y; b) { }
|
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* ```
|
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* the result is `int x = y;`.
|
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*
|
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* Does not hold if the initialization statement is missing or an empty statement, as in
|
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* ```
|
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* switch (b) { }
|
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* ```
|
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* or
|
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* ```
|
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* switch (; b) { }
|
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* ```
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*/
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Stmt getInitialization() {
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switch_initialization(underlyingElement(this), unresolveElement(result))
|
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}
|
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|
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/**
|
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* Gets the expression that this 'switch' statement switches on.
|
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*
|
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@@ -1485,7 +1549,7 @@ class SwitchStmt extends ConditionalStmt, @stmt_switch {
|
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* ```
|
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* the result is `i`.
|
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*/
|
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Expr getExpr() { result = this.getChild(0) }
|
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Expr getExpr() { result = this.getChild(1) }
|
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|
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override Expr getControllingExpr() { result = this.getExpr() }
|
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|
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|
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@@ -1863,6 +1863,11 @@ variable_vla(
|
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int decl: @stmt_vla_decl ref
|
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);
|
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|
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if_initialization(
|
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unique int if_stmt: @stmt_if ref,
|
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int init_id: @stmt ref
|
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);
|
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|
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if_then(
|
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unique int if_stmt: @stmt_if ref,
|
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int then_id: @stmt ref
|
||||
@@ -1873,6 +1878,11 @@ if_else(
|
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int else_id: @stmt ref
|
||||
);
|
||||
|
||||
constexpr_if_initialization(
|
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unique int constexpr_if_stmt: @stmt_constexpr_if ref,
|
||||
int init_id: @stmt ref
|
||||
);
|
||||
|
||||
constexpr_if_then(
|
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unique int constexpr_if_stmt: @stmt_constexpr_if ref,
|
||||
int then_id: @stmt ref
|
||||
@@ -1893,6 +1903,11 @@ do_body(
|
||||
int body_id: @stmt ref
|
||||
);
|
||||
|
||||
switch_initialization(
|
||||
unique int switch_stmt: @stmt_switch ref,
|
||||
int init_id: @stmt ref
|
||||
);
|
||||
|
||||
#keyset[switch_stmt, index]
|
||||
switch_case(
|
||||
int switch_stmt: @stmt_switch ref,
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,21 @@
|
||||
class Element extends @element {
|
||||
string toString() { none() }
|
||||
}
|
||||
|
||||
class Expr extends @expr {
|
||||
string toString() { none() }
|
||||
}
|
||||
|
||||
class Stmt extends @stmt {
|
||||
string toString() { none() }
|
||||
}
|
||||
|
||||
predicate isStmtWithInitializer(Stmt stmt) {
|
||||
exists(int kind | stmts(stmt, kind, _) | kind = 2 or kind = 11 or kind = 35)
|
||||
}
|
||||
|
||||
from Expr child, int index, int index_new, Element parent
|
||||
where
|
||||
exprparents(child, index, parent) and
|
||||
if isStmtWithInitializer(parent) then index_new = index + 1 else index_new = index
|
||||
select child, index_new, parent
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,17 @@
|
||||
class Element extends @element {
|
||||
string toString() { none() }
|
||||
}
|
||||
|
||||
class Stmt extends @stmt {
|
||||
string toString() { none() }
|
||||
}
|
||||
|
||||
predicate isStmtWithInitializer(Stmt stmt) {
|
||||
exists(int kind | stmts(stmt, kind, _) | kind = 2 or kind = 11 or kind = 35)
|
||||
}
|
||||
|
||||
from Stmt child, int index, int index_new, Element parent
|
||||
where
|
||||
stmtparents(child, index, parent) and
|
||||
if isStmtWithInitializer(parent) then index_new = index + 1 else index_new = index
|
||||
select child, index_new, parent
|
||||
@@ -0,0 +1,4 @@
|
||||
description: Support C++17 if and switch initializers
|
||||
compatibility: partial
|
||||
exprparents.rel: run exprparents.qlo
|
||||
stmtparents.rel: run stmtparents.qlo
|
||||
@@ -57,6 +57,5 @@ where
|
||||
not declarationHasSideEffects(v) and
|
||||
not exists(AsmStmt s | f = s.getEnclosingFunction()) and
|
||||
not v.getAnAttribute().getName() = "unused" and
|
||||
not any(ErrorExpr e).getEnclosingFunction() = f and // unextracted expr may use `v`
|
||||
not any(ConditionDeclExpr cde).getEnclosingFunction() = f // this case can be removed when the `if (a = b; a)` and `switch (a = b; a)` test cases don't depend on this exclusion
|
||||
not any(ErrorExpr e).getEnclosingFunction() = f // unextracted expr may use `v`
|
||||
select v, "Variable " + v.getName() + " is not used"
|
||||
|
||||
@@ -0,0 +1,4 @@
|
||||
---
|
||||
category: minorAnalysis
|
||||
---
|
||||
* The `cpp/unused-local-variable` no longer ignores functions that include `if` and `switch` statements with C++17-style initializers.
|
||||
@@ -13559,6 +13559,422 @@ ir.cpp:
|
||||
# 1754| Type = [SpecifiedType] const CopyConstructorTestVirtualClass
|
||||
# 1754| ValueCategory = lvalue
|
||||
# 1755| getStmt(2): [ReturnStmt] return ...
|
||||
# 1757| [TopLevelFunction] void if_initialization(int)
|
||||
# 1757| <params>:
|
||||
# 1757| getParameter(0): [Parameter] x
|
||||
# 1757| Type = [IntType] int
|
||||
# 1757| getEntryPoint(): [BlockStmt] { ... }
|
||||
# 1758| getStmt(0): [IfStmt] if (...) ...
|
||||
# 1758| getInitialization(): [DeclStmt] declaration
|
||||
# 1758| getDeclarationEntry(0): [VariableDeclarationEntry] definition of y
|
||||
# 1758| Type = [IntType] int
|
||||
# 1758| getVariable().getInitializer(): [Initializer] initializer for y
|
||||
# 1758| getExpr(): [VariableAccess] x
|
||||
# 1758| Type = [IntType] int
|
||||
# 1758| ValueCategory = prvalue(load)
|
||||
# 1758| getCondition(): [AddExpr] ... + ...
|
||||
# 1758| Type = [IntType] int
|
||||
# 1758| ValueCategory = prvalue
|
||||
# 1758| getLeftOperand(): [VariableAccess] x
|
||||
# 1758| Type = [IntType] int
|
||||
# 1758| ValueCategory = prvalue(load)
|
||||
# 1758| getRightOperand(): [Literal] 1
|
||||
# 1758| Type = [IntType] int
|
||||
# 1758| Value = [Literal] 1
|
||||
# 1758| ValueCategory = prvalue
|
||||
# 1758| getThen(): [BlockStmt] { ... }
|
||||
# 1759| getStmt(0): [ExprStmt] ExprStmt
|
||||
# 1759| getExpr(): [AssignExpr] ... = ...
|
||||
# 1759| Type = [IntType] int
|
||||
# 1759| ValueCategory = lvalue
|
||||
# 1759| getLValue(): [VariableAccess] x
|
||||
# 1759| Type = [IntType] int
|
||||
# 1759| ValueCategory = lvalue
|
||||
# 1759| getRValue(): [AddExpr] ... + ...
|
||||
# 1759| Type = [IntType] int
|
||||
# 1759| ValueCategory = prvalue
|
||||
# 1759| getLeftOperand(): [VariableAccess] x
|
||||
# 1759| Type = [IntType] int
|
||||
# 1759| ValueCategory = prvalue(load)
|
||||
# 1759| getRightOperand(): [VariableAccess] y
|
||||
# 1759| Type = [IntType] int
|
||||
# 1759| ValueCategory = prvalue(load)
|
||||
# 1758| getCondition().getFullyConverted(): [CStyleCast] (bool)...
|
||||
# 1758| Conversion = [BoolConversion] conversion to bool
|
||||
# 1758| Type = [BoolType] bool
|
||||
# 1758| ValueCategory = prvalue
|
||||
# 1762| getStmt(1): [DeclStmt] declaration
|
||||
# 1762| getDeclarationEntry(0): [VariableDeclarationEntry] definition of w
|
||||
# 1762| Type = [IntType] int
|
||||
# 1763| getStmt(2): [IfStmt] if (...) ...
|
||||
# 1763| getInitialization(): [ExprStmt] ExprStmt
|
||||
# 1763| getExpr(): [AssignExpr] ... = ...
|
||||
# 1763| Type = [IntType] int
|
||||
# 1763| ValueCategory = lvalue
|
||||
# 1763| getLValue(): [VariableAccess] w
|
||||
# 1763| Type = [IntType] int
|
||||
# 1763| ValueCategory = lvalue
|
||||
# 1763| getRValue(): [VariableAccess] x
|
||||
# 1763| Type = [IntType] int
|
||||
# 1763| ValueCategory = prvalue(load)
|
||||
# 1763| getCondition(): [AddExpr] ... + ...
|
||||
# 1763| Type = [IntType] int
|
||||
# 1763| ValueCategory = prvalue
|
||||
# 1763| getLeftOperand(): [VariableAccess] x
|
||||
# 1763| Type = [IntType] int
|
||||
# 1763| ValueCategory = prvalue(load)
|
||||
# 1763| getRightOperand(): [Literal] 1
|
||||
# 1763| Type = [IntType] int
|
||||
# 1763| Value = [Literal] 1
|
||||
# 1763| ValueCategory = prvalue
|
||||
# 1763| getThen(): [BlockStmt] { ... }
|
||||
# 1764| getStmt(0): [ExprStmt] ExprStmt
|
||||
# 1764| getExpr(): [AssignExpr] ... = ...
|
||||
# 1764| Type = [IntType] int
|
||||
# 1764| ValueCategory = lvalue
|
||||
# 1764| getLValue(): [VariableAccess] x
|
||||
# 1764| Type = [IntType] int
|
||||
# 1764| ValueCategory = lvalue
|
||||
# 1764| getRValue(): [AddExpr] ... + ...
|
||||
# 1764| Type = [IntType] int
|
||||
# 1764| ValueCategory = prvalue
|
||||
# 1764| getLeftOperand(): [VariableAccess] x
|
||||
# 1764| Type = [IntType] int
|
||||
# 1764| ValueCategory = prvalue(load)
|
||||
# 1764| getRightOperand(): [VariableAccess] w
|
||||
# 1764| Type = [IntType] int
|
||||
# 1764| ValueCategory = prvalue(load)
|
||||
# 1763| getCondition().getFullyConverted(): [CStyleCast] (bool)...
|
||||
# 1763| Conversion = [BoolConversion] conversion to bool
|
||||
# 1763| Type = [BoolType] bool
|
||||
# 1763| ValueCategory = prvalue
|
||||
# 1767| getStmt(3): [IfStmt] if (...) ...
|
||||
# 1767| getInitialization(): [ExprStmt] ExprStmt
|
||||
# 1767| getExpr(): [AssignExpr] ... = ...
|
||||
# 1767| Type = [IntType] int
|
||||
# 1767| ValueCategory = lvalue
|
||||
# 1767| getLValue(): [VariableAccess] w
|
||||
# 1767| Type = [IntType] int
|
||||
# 1767| ValueCategory = lvalue
|
||||
# 1767| getRValue(): [VariableAccess] x
|
||||
# 1767| Type = [IntType] int
|
||||
# 1767| ValueCategory = prvalue(load)
|
||||
# 1767| getCondition(): [ConditionDeclExpr] (condition decl)
|
||||
# 1767| Type = [BoolType] bool
|
||||
# 1767| ValueCategory = prvalue
|
||||
# 1767| getVariableAccess(): [VariableAccess] w2
|
||||
# 1767| Type = [IntType] int
|
||||
# 1767| ValueCategory = prvalue(load)
|
||||
# 1767| getVariableAccess().getFullyConverted(): [CStyleCast] (bool)...
|
||||
# 1767| Conversion = [BoolConversion] conversion to bool
|
||||
# 1767| Type = [BoolType] bool
|
||||
# 1767| ValueCategory = prvalue
|
||||
# 1767| getThen(): [BlockStmt] { ... }
|
||||
# 1768| getStmt(0): [ExprStmt] ExprStmt
|
||||
# 1768| getExpr(): [AssignExpr] ... = ...
|
||||
# 1768| Type = [IntType] int
|
||||
# 1768| ValueCategory = lvalue
|
||||
# 1768| getLValue(): [VariableAccess] x
|
||||
# 1768| Type = [IntType] int
|
||||
# 1768| ValueCategory = lvalue
|
||||
# 1768| getRValue(): [AddExpr] ... + ...
|
||||
# 1768| Type = [IntType] int
|
||||
# 1768| ValueCategory = prvalue
|
||||
# 1768| getLeftOperand(): [VariableAccess] x
|
||||
# 1768| Type = [IntType] int
|
||||
# 1768| ValueCategory = prvalue(load)
|
||||
# 1768| getRightOperand(): [VariableAccess] w
|
||||
# 1768| Type = [IntType] int
|
||||
# 1768| ValueCategory = prvalue(load)
|
||||
# 1771| getStmt(4): [IfStmt] if (...) ...
|
||||
# 1771| getInitialization(): [DeclStmt] declaration
|
||||
# 1771| getDeclarationEntry(0): [VariableDeclarationEntry] definition of v
|
||||
# 1771| Type = [IntType] int
|
||||
# 1771| getVariable().getInitializer(): [Initializer] initializer for v
|
||||
# 1771| getExpr(): [VariableAccess] x
|
||||
# 1771| Type = [IntType] int
|
||||
# 1771| ValueCategory = prvalue(load)
|
||||
# 1771| getCondition(): [ConditionDeclExpr] (condition decl)
|
||||
# 1771| Type = [BoolType] bool
|
||||
# 1771| ValueCategory = prvalue
|
||||
# 1771| getVariableAccess(): [VariableAccess] v2
|
||||
# 1771| Type = [IntType] int
|
||||
# 1771| ValueCategory = prvalue(load)
|
||||
# 1771| getVariableAccess().getFullyConverted(): [CStyleCast] (bool)...
|
||||
# 1771| Conversion = [BoolConversion] conversion to bool
|
||||
# 1771| Type = [BoolType] bool
|
||||
# 1771| ValueCategory = prvalue
|
||||
# 1771| getThen(): [BlockStmt] { ... }
|
||||
# 1772| getStmt(0): [ExprStmt] ExprStmt
|
||||
# 1772| getExpr(): [AssignExpr] ... = ...
|
||||
# 1772| Type = [IntType] int
|
||||
# 1772| ValueCategory = lvalue
|
||||
# 1772| getLValue(): [VariableAccess] x
|
||||
# 1772| Type = [IntType] int
|
||||
# 1772| ValueCategory = lvalue
|
||||
# 1772| getRValue(): [AddExpr] ... + ...
|
||||
# 1772| Type = [IntType] int
|
||||
# 1772| ValueCategory = prvalue
|
||||
# 1772| getLeftOperand(): [VariableAccess] x
|
||||
# 1772| Type = [IntType] int
|
||||
# 1772| ValueCategory = prvalue(load)
|
||||
# 1772| getRightOperand(): [VariableAccess] v
|
||||
# 1772| Type = [IntType] int
|
||||
# 1772| ValueCategory = prvalue(load)
|
||||
# 1775| getStmt(5): [DeclStmt] declaration
|
||||
# 1775| getDeclarationEntry(0): [VariableDeclarationEntry] definition of z
|
||||
# 1775| Type = [IntType] int
|
||||
# 1775| getVariable().getInitializer(): [Initializer] initializer for z
|
||||
# 1775| getExpr(): [VariableAccess] x
|
||||
# 1775| Type = [IntType] int
|
||||
# 1775| ValueCategory = prvalue(load)
|
||||
# 1776| getStmt(6): [IfStmt] if (...) ...
|
||||
# 1776| getCondition(): [VariableAccess] z
|
||||
# 1776| Type = [IntType] int
|
||||
# 1776| ValueCategory = prvalue(load)
|
||||
# 1776| getThen(): [BlockStmt] { ... }
|
||||
# 1777| getStmt(0): [ExprStmt] ExprStmt
|
||||
# 1777| getExpr(): [AssignExpr] ... = ...
|
||||
# 1777| Type = [IntType] int
|
||||
# 1777| ValueCategory = lvalue
|
||||
# 1777| getLValue(): [VariableAccess] x
|
||||
# 1777| Type = [IntType] int
|
||||
# 1777| ValueCategory = lvalue
|
||||
# 1777| getRValue(): [AddExpr] ... + ...
|
||||
# 1777| Type = [IntType] int
|
||||
# 1777| ValueCategory = prvalue
|
||||
# 1777| getLeftOperand(): [VariableAccess] x
|
||||
# 1777| Type = [IntType] int
|
||||
# 1777| ValueCategory = prvalue(load)
|
||||
# 1777| getRightOperand(): [VariableAccess] z
|
||||
# 1777| Type = [IntType] int
|
||||
# 1777| ValueCategory = prvalue(load)
|
||||
# 1776| getCondition().getFullyConverted(): [CStyleCast] (bool)...
|
||||
# 1776| Conversion = [BoolConversion] conversion to bool
|
||||
# 1776| Type = [BoolType] bool
|
||||
# 1776| ValueCategory = prvalue
|
||||
# 1780| getStmt(7): [IfStmt] if (...) ...
|
||||
# 1780| getCondition(): [ConditionDeclExpr] (condition decl)
|
||||
# 1780| Type = [BoolType] bool
|
||||
# 1780| ValueCategory = prvalue
|
||||
# 1780| getVariableAccess(): [VariableAccess] z2
|
||||
# 1780| Type = [IntType] int
|
||||
# 1780| ValueCategory = prvalue(load)
|
||||
# 1780| getVariableAccess().getFullyConverted(): [CStyleCast] (bool)...
|
||||
# 1780| Conversion = [BoolConversion] conversion to bool
|
||||
# 1780| Type = [BoolType] bool
|
||||
# 1780| ValueCategory = prvalue
|
||||
# 1780| getThen(): [BlockStmt] { ... }
|
||||
# 1781| getStmt(0): [ExprStmt] ExprStmt
|
||||
# 1781| getExpr(): [AssignAddExpr] ... += ...
|
||||
# 1781| Type = [IntType] int
|
||||
# 1781| ValueCategory = lvalue
|
||||
# 1781| getLValue(): [VariableAccess] x
|
||||
# 1781| Type = [IntType] int
|
||||
# 1781| ValueCategory = lvalue
|
||||
# 1781| getRValue(): [VariableAccess] z2
|
||||
# 1781| Type = [IntType] int
|
||||
# 1781| ValueCategory = prvalue(load)
|
||||
# 1783| getStmt(8): [ReturnStmt] return ...
|
||||
# 1785| [TopLevelFunction] void switch_initialization(int)
|
||||
# 1785| <params>:
|
||||
# 1785| getParameter(0): [Parameter] x
|
||||
# 1785| Type = [IntType] int
|
||||
# 1785| getEntryPoint(): [BlockStmt] { ... }
|
||||
# 1786| getStmt(0): [SwitchStmt] switch (...) ...
|
||||
# 1786| getInitialization(): [DeclStmt] declaration
|
||||
# 1786| getDeclarationEntry(0): [VariableDeclarationEntry] definition of y
|
||||
# 1786| Type = [IntType] int
|
||||
# 1786| getVariable().getInitializer(): [Initializer] initializer for y
|
||||
# 1786| getExpr(): [VariableAccess] x
|
||||
# 1786| Type = [IntType] int
|
||||
# 1786| ValueCategory = prvalue(load)
|
||||
# 1786| getExpr(): [AddExpr] ... + ...
|
||||
# 1786| Type = [IntType] int
|
||||
# 1786| ValueCategory = prvalue
|
||||
# 1786| getLeftOperand(): [VariableAccess] x
|
||||
# 1786| Type = [IntType] int
|
||||
# 1786| ValueCategory = prvalue(load)
|
||||
# 1786| getRightOperand(): [Literal] 1
|
||||
# 1786| Type = [IntType] int
|
||||
# 1786| Value = [Literal] 1
|
||||
# 1786| ValueCategory = prvalue
|
||||
# 1786| getStmt(): [BlockStmt] { ... }
|
||||
# 1787| getStmt(0): [SwitchCase] default:
|
||||
# 1788| getStmt(1): [ExprStmt] ExprStmt
|
||||
# 1788| getExpr(): [AssignExpr] ... = ...
|
||||
# 1788| Type = [IntType] int
|
||||
# 1788| ValueCategory = lvalue
|
||||
# 1788| getLValue(): [VariableAccess] x
|
||||
# 1788| Type = [IntType] int
|
||||
# 1788| ValueCategory = lvalue
|
||||
# 1788| getRValue(): [AddExpr] ... + ...
|
||||
# 1788| Type = [IntType] int
|
||||
# 1788| ValueCategory = prvalue
|
||||
# 1788| getLeftOperand(): [VariableAccess] x
|
||||
# 1788| Type = [IntType] int
|
||||
# 1788| ValueCategory = prvalue(load)
|
||||
# 1788| getRightOperand(): [VariableAccess] y
|
||||
# 1788| Type = [IntType] int
|
||||
# 1788| ValueCategory = prvalue(load)
|
||||
# 1791| getStmt(1): [DeclStmt] declaration
|
||||
# 1791| getDeclarationEntry(0): [VariableDeclarationEntry] definition of w
|
||||
# 1791| Type = [IntType] int
|
||||
# 1792| getStmt(2): [SwitchStmt] switch (...) ...
|
||||
# 1792| getInitialization(): [ExprStmt] ExprStmt
|
||||
# 1792| getExpr(): [AssignExpr] ... = ...
|
||||
# 1792| Type = [IntType] int
|
||||
# 1792| ValueCategory = lvalue
|
||||
# 1792| getLValue(): [VariableAccess] w
|
||||
# 1792| Type = [IntType] int
|
||||
# 1792| ValueCategory = lvalue
|
||||
# 1792| getRValue(): [VariableAccess] x
|
||||
# 1792| Type = [IntType] int
|
||||
# 1792| ValueCategory = prvalue(load)
|
||||
# 1792| getExpr(): [AddExpr] ... + ...
|
||||
# 1792| Type = [IntType] int
|
||||
# 1792| ValueCategory = prvalue
|
||||
# 1792| getLeftOperand(): [VariableAccess] x
|
||||
# 1792| Type = [IntType] int
|
||||
# 1792| ValueCategory = prvalue(load)
|
||||
# 1792| getRightOperand(): [Literal] 1
|
||||
# 1792| Type = [IntType] int
|
||||
# 1792| Value = [Literal] 1
|
||||
# 1792| ValueCategory = prvalue
|
||||
# 1792| getStmt(): [BlockStmt] { ... }
|
||||
# 1793| getStmt(0): [SwitchCase] default:
|
||||
# 1794| getStmt(1): [ExprStmt] ExprStmt
|
||||
# 1794| getExpr(): [AssignExpr] ... = ...
|
||||
# 1794| Type = [IntType] int
|
||||
# 1794| ValueCategory = lvalue
|
||||
# 1794| getLValue(): [VariableAccess] x
|
||||
# 1794| Type = [IntType] int
|
||||
# 1794| ValueCategory = lvalue
|
||||
# 1794| getRValue(): [AddExpr] ... + ...
|
||||
# 1794| Type = [IntType] int
|
||||
# 1794| ValueCategory = prvalue
|
||||
# 1794| getLeftOperand(): [VariableAccess] x
|
||||
# 1794| Type = [IntType] int
|
||||
# 1794| ValueCategory = prvalue(load)
|
||||
# 1794| getRightOperand(): [VariableAccess] w
|
||||
# 1794| Type = [IntType] int
|
||||
# 1794| ValueCategory = prvalue(load)
|
||||
# 1797| getStmt(3): [SwitchStmt] switch (...) ...
|
||||
# 1797| getInitialization(): [ExprStmt] ExprStmt
|
||||
# 1797| getExpr(): [AssignExpr] ... = ...
|
||||
# 1797| Type = [IntType] int
|
||||
# 1797| ValueCategory = lvalue
|
||||
# 1797| getLValue(): [VariableAccess] w
|
||||
# 1797| Type = [IntType] int
|
||||
# 1797| ValueCategory = lvalue
|
||||
# 1797| getRValue(): [VariableAccess] x
|
||||
# 1797| Type = [IntType] int
|
||||
# 1797| ValueCategory = prvalue(load)
|
||||
# 1797| getExpr(): [ConditionDeclExpr] (condition decl)
|
||||
# 1797| Type = [IntType] int
|
||||
# 1797| ValueCategory = prvalue
|
||||
# 1797| getVariableAccess(): [VariableAccess] w2
|
||||
# 1797| Type = [IntType] int
|
||||
# 1797| ValueCategory = prvalue(load)
|
||||
# 1797| getStmt(): [BlockStmt] { ... }
|
||||
# 1798| getStmt(0): [SwitchCase] default:
|
||||
# 1799| getStmt(1): [ExprStmt] ExprStmt
|
||||
# 1799| getExpr(): [AssignExpr] ... = ...
|
||||
# 1799| Type = [IntType] int
|
||||
# 1799| ValueCategory = lvalue
|
||||
# 1799| getLValue(): [VariableAccess] x
|
||||
# 1799| Type = [IntType] int
|
||||
# 1799| ValueCategory = lvalue
|
||||
# 1799| getRValue(): [AddExpr] ... + ...
|
||||
# 1799| Type = [IntType] int
|
||||
# 1799| ValueCategory = prvalue
|
||||
# 1799| getLeftOperand(): [VariableAccess] x
|
||||
# 1799| Type = [IntType] int
|
||||
# 1799| ValueCategory = prvalue(load)
|
||||
# 1799| getRightOperand(): [VariableAccess] w
|
||||
# 1799| Type = [IntType] int
|
||||
# 1799| ValueCategory = prvalue(load)
|
||||
# 1802| getStmt(4): [SwitchStmt] switch (...) ...
|
||||
# 1802| getInitialization(): [DeclStmt] declaration
|
||||
# 1802| getDeclarationEntry(0): [VariableDeclarationEntry] definition of v
|
||||
# 1802| Type = [IntType] int
|
||||
# 1802| getVariable().getInitializer(): [Initializer] initializer for v
|
||||
# 1802| getExpr(): [VariableAccess] x
|
||||
# 1802| Type = [IntType] int
|
||||
# 1802| ValueCategory = prvalue(load)
|
||||
# 1802| getExpr(): [ConditionDeclExpr] (condition decl)
|
||||
# 1802| Type = [IntType] int
|
||||
# 1802| ValueCategory = prvalue
|
||||
# 1802| getVariableAccess(): [VariableAccess] v2
|
||||
# 1802| Type = [IntType] int
|
||||
# 1802| ValueCategory = prvalue(load)
|
||||
# 1802| getStmt(): [BlockStmt] { ... }
|
||||
# 1803| getStmt(0): [SwitchCase] default:
|
||||
# 1804| getStmt(1): [ExprStmt] ExprStmt
|
||||
# 1804| getExpr(): [AssignExpr] ... = ...
|
||||
# 1804| Type = [IntType] int
|
||||
# 1804| ValueCategory = lvalue
|
||||
# 1804| getLValue(): [VariableAccess] x
|
||||
# 1804| Type = [IntType] int
|
||||
# 1804| ValueCategory = lvalue
|
||||
# 1804| getRValue(): [AddExpr] ... + ...
|
||||
# 1804| Type = [IntType] int
|
||||
# 1804| ValueCategory = prvalue
|
||||
# 1804| getLeftOperand(): [VariableAccess] x
|
||||
# 1804| Type = [IntType] int
|
||||
# 1804| ValueCategory = prvalue(load)
|
||||
# 1804| getRightOperand(): [VariableAccess] v
|
||||
# 1804| Type = [IntType] int
|
||||
# 1804| ValueCategory = prvalue(load)
|
||||
# 1807| getStmt(5): [DeclStmt] declaration
|
||||
# 1807| getDeclarationEntry(0): [VariableDeclarationEntry] definition of z
|
||||
# 1807| Type = [IntType] int
|
||||
# 1807| getVariable().getInitializer(): [Initializer] initializer for z
|
||||
# 1807| getExpr(): [VariableAccess] x
|
||||
# 1807| Type = [IntType] int
|
||||
# 1807| ValueCategory = prvalue(load)
|
||||
# 1808| getStmt(6): [SwitchStmt] switch (...) ...
|
||||
# 1808| getExpr(): [VariableAccess] z
|
||||
# 1808| Type = [IntType] int
|
||||
# 1808| ValueCategory = prvalue(load)
|
||||
# 1808| getStmt(): [BlockStmt] { ... }
|
||||
# 1809| getStmt(0): [SwitchCase] default:
|
||||
# 1810| getStmt(1): [ExprStmt] ExprStmt
|
||||
# 1810| getExpr(): [AssignExpr] ... = ...
|
||||
# 1810| Type = [IntType] int
|
||||
# 1810| ValueCategory = lvalue
|
||||
# 1810| getLValue(): [VariableAccess] x
|
||||
# 1810| Type = [IntType] int
|
||||
# 1810| ValueCategory = lvalue
|
||||
# 1810| getRValue(): [AddExpr] ... + ...
|
||||
# 1810| Type = [IntType] int
|
||||
# 1810| ValueCategory = prvalue
|
||||
# 1810| getLeftOperand(): [VariableAccess] x
|
||||
# 1810| Type = [IntType] int
|
||||
# 1810| ValueCategory = prvalue(load)
|
||||
# 1810| getRightOperand(): [VariableAccess] z
|
||||
# 1810| Type = [IntType] int
|
||||
# 1810| ValueCategory = prvalue(load)
|
||||
# 1813| getStmt(7): [SwitchStmt] switch (...) ...
|
||||
# 1813| getExpr(): [ConditionDeclExpr] (condition decl)
|
||||
# 1813| Type = [IntType] int
|
||||
# 1813| ValueCategory = prvalue
|
||||
# 1813| getVariableAccess(): [VariableAccess] z2
|
||||
# 1813| Type = [IntType] int
|
||||
# 1813| ValueCategory = prvalue(load)
|
||||
# 1813| getStmt(): [BlockStmt] { ... }
|
||||
# 1814| getStmt(0): [SwitchCase] default:
|
||||
# 1815| getStmt(1): [ExprStmt] ExprStmt
|
||||
# 1815| getExpr(): [AssignAddExpr] ... += ...
|
||||
# 1815| Type = [IntType] int
|
||||
# 1815| ValueCategory = lvalue
|
||||
# 1815| getLValue(): [VariableAccess] x
|
||||
# 1815| Type = [IntType] int
|
||||
# 1815| ValueCategory = lvalue
|
||||
# 1815| getRValue(): [VariableAccess] z2
|
||||
# 1815| Type = [IntType] int
|
||||
# 1815| ValueCategory = prvalue(load)
|
||||
# 1817| getStmt(8): [ReturnStmt] return ...
|
||||
perf-regression.cpp:
|
||||
# 4| [CopyAssignmentOperator] Big& Big::operator=(Big const&)
|
||||
# 4| <params>:
|
||||
|
||||
@@ -1754,4 +1754,66 @@ int implicit_copy_constructor_test(
|
||||
CopyConstructorTestVirtualClass cy = y;
|
||||
}
|
||||
|
||||
void if_initialization(int x) {
|
||||
if (int y = x; x + 1) {
|
||||
x = x + y;
|
||||
}
|
||||
|
||||
int w;
|
||||
if (w = x; x + 1) {
|
||||
x = x + w;
|
||||
}
|
||||
|
||||
if (w = x; int w2 = w) {
|
||||
x = x + w;
|
||||
}
|
||||
|
||||
if (int v = x; int v2 = v) {
|
||||
x = x + v;
|
||||
}
|
||||
|
||||
int z = x;
|
||||
if (z) {
|
||||
x = x + z;
|
||||
}
|
||||
|
||||
if (int z2 = z) {
|
||||
x += z2;
|
||||
}
|
||||
}
|
||||
|
||||
void switch_initialization(int x) {
|
||||
switch (int y = x; x + 1) {
|
||||
default:
|
||||
x = x + y;
|
||||
}
|
||||
|
||||
int w;
|
||||
switch (w = x; x + 1) {
|
||||
default:
|
||||
x = x + w;
|
||||
}
|
||||
|
||||
switch (w = x; int w2 = w) {
|
||||
default:
|
||||
x = x + w;
|
||||
}
|
||||
|
||||
switch (int v = x; int v2 = v) {
|
||||
default:
|
||||
x = x + v;
|
||||
}
|
||||
|
||||
int z = x;
|
||||
switch (z) {
|
||||
default:
|
||||
x = x + z;
|
||||
}
|
||||
|
||||
switch (int z2 = z) {
|
||||
default:
|
||||
x += z2;
|
||||
}
|
||||
}
|
||||
|
||||
// semmle-extractor-options: -std=c++17 --clang
|
||||
|
||||
@@ -8215,6 +8215,248 @@
|
||||
| ir.cpp:1754:42:1754:42 | SideEffect | ~m1752_4 |
|
||||
| ir.cpp:1754:42:1754:42 | Unary | r1754_5 |
|
||||
| ir.cpp:1754:42:1754:42 | Unary | r1754_6 |
|
||||
| ir.cpp:1757:6:1757:22 | ChiPartial | partial:m1757_3 |
|
||||
| ir.cpp:1757:6:1757:22 | ChiTotal | total:m1757_2 |
|
||||
| ir.cpp:1757:6:1757:22 | SideEffect | m1757_3 |
|
||||
| ir.cpp:1757:28:1757:28 | Address | &:r1757_5 |
|
||||
| ir.cpp:1758:13:1758:13 | Address | &:r1758_1 |
|
||||
| ir.cpp:1758:17:1758:17 | Address | &:r1758_2 |
|
||||
| ir.cpp:1758:17:1758:17 | Load | m1757_6 |
|
||||
| ir.cpp:1758:17:1758:17 | StoreValue | r1758_3 |
|
||||
| ir.cpp:1758:20:1758:20 | Address | &:r1758_5 |
|
||||
| ir.cpp:1758:20:1758:20 | Left | r1758_6 |
|
||||
| ir.cpp:1758:20:1758:20 | Load | m1757_6 |
|
||||
| ir.cpp:1758:20:1758:24 | Condition | r1758_10 |
|
||||
| ir.cpp:1758:20:1758:24 | Left | r1758_8 |
|
||||
| ir.cpp:1758:20:1758:24 | Right | r1758_9 |
|
||||
| ir.cpp:1758:24:1758:24 | Right | r1758_7 |
|
||||
| ir.cpp:1759:9:1759:9 | Address | &:r1759_6 |
|
||||
| ir.cpp:1759:13:1759:13 | Address | &:r1759_1 |
|
||||
| ir.cpp:1759:13:1759:13 | Left | r1759_2 |
|
||||
| ir.cpp:1759:13:1759:13 | Load | m1757_6 |
|
||||
| ir.cpp:1759:13:1759:17 | StoreValue | r1759_5 |
|
||||
| ir.cpp:1759:17:1759:17 | Address | &:r1759_3 |
|
||||
| ir.cpp:1759:17:1759:17 | Load | m1758_4 |
|
||||
| ir.cpp:1759:17:1759:17 | Right | r1759_4 |
|
||||
| ir.cpp:1762:9:1762:9 | Address | &:r1762_2 |
|
||||
| ir.cpp:1762:9:1762:9 | Phi | from 0:m1757_6 |
|
||||
| ir.cpp:1762:9:1762:9 | Phi | from 1:m1759_7 |
|
||||
| ir.cpp:1763:9:1763:9 | Address | &:r1763_3 |
|
||||
| ir.cpp:1763:13:1763:13 | Address | &:r1763_1 |
|
||||
| ir.cpp:1763:13:1763:13 | Load | m1762_1 |
|
||||
| ir.cpp:1763:13:1763:13 | StoreValue | r1763_2 |
|
||||
| ir.cpp:1763:16:1763:16 | Address | &:r1763_5 |
|
||||
| ir.cpp:1763:16:1763:16 | Left | r1763_6 |
|
||||
| ir.cpp:1763:16:1763:16 | Load | m1762_1 |
|
||||
| ir.cpp:1763:16:1763:20 | Condition | r1763_10 |
|
||||
| ir.cpp:1763:16:1763:20 | Left | r1763_8 |
|
||||
| ir.cpp:1763:16:1763:20 | Right | r1763_9 |
|
||||
| ir.cpp:1763:20:1763:20 | Right | r1763_7 |
|
||||
| ir.cpp:1764:9:1764:9 | Address | &:r1764_6 |
|
||||
| ir.cpp:1764:13:1764:13 | Address | &:r1764_1 |
|
||||
| ir.cpp:1764:13:1764:13 | Left | r1764_2 |
|
||||
| ir.cpp:1764:13:1764:13 | Load | m1762_1 |
|
||||
| ir.cpp:1764:13:1764:17 | StoreValue | r1764_5 |
|
||||
| ir.cpp:1764:17:1764:17 | Address | &:r1764_3 |
|
||||
| ir.cpp:1764:17:1764:17 | Load | m1763_4 |
|
||||
| ir.cpp:1764:17:1764:17 | Right | r1764_4 |
|
||||
| ir.cpp:1767:9:1767:9 | Address | &:r1767_4 |
|
||||
| ir.cpp:1767:13:1767:13 | Address | &:r1767_2 |
|
||||
| ir.cpp:1767:13:1767:13 | Load | m1767_1 |
|
||||
| ir.cpp:1767:13:1767:13 | Phi | from 2:m1762_1 |
|
||||
| ir.cpp:1767:13:1767:13 | Phi | from 3:m1764_7 |
|
||||
| ir.cpp:1767:13:1767:13 | StoreValue | r1767_3 |
|
||||
| ir.cpp:1767:14:1767:25 | Address | &:r1767_6 |
|
||||
| ir.cpp:1767:14:1767:25 | Condition | r1767_14 |
|
||||
| ir.cpp:1767:20:1767:21 | Address | &:r1767_10 |
|
||||
| ir.cpp:1767:20:1767:21 | Left | r1767_11 |
|
||||
| ir.cpp:1767:20:1767:21 | Load | m1767_9 |
|
||||
| ir.cpp:1767:20:1767:21 | Right | r1767_12 |
|
||||
| ir.cpp:1767:20:1767:21 | Unary | r1767_13 |
|
||||
| ir.cpp:1767:25:1767:25 | Address | &:r1767_7 |
|
||||
| ir.cpp:1767:25:1767:25 | Load | m1767_5 |
|
||||
| ir.cpp:1767:25:1767:25 | StoreValue | r1767_8 |
|
||||
| ir.cpp:1768:9:1768:9 | Address | &:r1768_6 |
|
||||
| ir.cpp:1768:13:1768:13 | Address | &:r1768_1 |
|
||||
| ir.cpp:1768:13:1768:13 | Left | r1768_2 |
|
||||
| ir.cpp:1768:13:1768:13 | Load | m1767_1 |
|
||||
| ir.cpp:1768:13:1768:17 | StoreValue | r1768_5 |
|
||||
| ir.cpp:1768:17:1768:17 | Address | &:r1768_3 |
|
||||
| ir.cpp:1768:17:1768:17 | Load | m1767_5 |
|
||||
| ir.cpp:1768:17:1768:17 | Right | r1768_4 |
|
||||
| ir.cpp:1771:9:1771:29 | Address | &:r1771_6 |
|
||||
| ir.cpp:1771:9:1771:29 | Condition | r1771_14 |
|
||||
| ir.cpp:1771:13:1771:13 | Address | &:r1771_2 |
|
||||
| ir.cpp:1771:13:1771:13 | Phi | from 4:m1767_1 |
|
||||
| ir.cpp:1771:13:1771:13 | Phi | from 5:m1768_7 |
|
||||
| ir.cpp:1771:17:1771:17 | Address | &:r1771_3 |
|
||||
| ir.cpp:1771:17:1771:17 | Load | m1771_1 |
|
||||
| ir.cpp:1771:17:1771:17 | StoreValue | r1771_4 |
|
||||
| ir.cpp:1771:24:1771:25 | Address | &:r1771_10 |
|
||||
| ir.cpp:1771:24:1771:25 | Left | r1771_11 |
|
||||
| ir.cpp:1771:24:1771:25 | Load | m1771_9 |
|
||||
| ir.cpp:1771:24:1771:25 | Right | r1771_12 |
|
||||
| ir.cpp:1771:24:1771:25 | Unary | r1771_13 |
|
||||
| ir.cpp:1771:29:1771:29 | Address | &:r1771_7 |
|
||||
| ir.cpp:1771:29:1771:29 | Load | m1771_5 |
|
||||
| ir.cpp:1771:29:1771:29 | StoreValue | r1771_8 |
|
||||
| ir.cpp:1772:9:1772:9 | Address | &:r1772_6 |
|
||||
| ir.cpp:1772:13:1772:13 | Address | &:r1772_1 |
|
||||
| ir.cpp:1772:13:1772:13 | Left | r1772_2 |
|
||||
| ir.cpp:1772:13:1772:13 | Load | m1771_1 |
|
||||
| ir.cpp:1772:13:1772:17 | StoreValue | r1772_5 |
|
||||
| ir.cpp:1772:17:1772:17 | Address | &:r1772_3 |
|
||||
| ir.cpp:1772:17:1772:17 | Load | m1771_5 |
|
||||
| ir.cpp:1772:17:1772:17 | Right | r1772_4 |
|
||||
| ir.cpp:1775:9:1775:9 | Address | &:r1775_2 |
|
||||
| ir.cpp:1775:9:1775:9 | Phi | from 6:m1771_1 |
|
||||
| ir.cpp:1775:9:1775:9 | Phi | from 7:m1772_7 |
|
||||
| ir.cpp:1775:13:1775:13 | Address | &:r1775_3 |
|
||||
| ir.cpp:1775:13:1775:13 | Load | m1775_1 |
|
||||
| ir.cpp:1775:13:1775:13 | StoreValue | r1775_4 |
|
||||
| ir.cpp:1776:9:1776:9 | Address | &:r1776_1 |
|
||||
| ir.cpp:1776:9:1776:9 | Condition | r1776_4 |
|
||||
| ir.cpp:1776:9:1776:9 | Left | r1776_2 |
|
||||
| ir.cpp:1776:9:1776:9 | Load | m1775_5 |
|
||||
| ir.cpp:1776:9:1776:9 | Right | r1776_3 |
|
||||
| ir.cpp:1777:9:1777:9 | Address | &:r1777_6 |
|
||||
| ir.cpp:1777:13:1777:13 | Address | &:r1777_1 |
|
||||
| ir.cpp:1777:13:1777:13 | Left | r1777_2 |
|
||||
| ir.cpp:1777:13:1777:13 | Load | m1775_1 |
|
||||
| ir.cpp:1777:13:1777:17 | StoreValue | r1777_5 |
|
||||
| ir.cpp:1777:17:1777:17 | Address | &:r1777_3 |
|
||||
| ir.cpp:1777:17:1777:17 | Load | m1775_5 |
|
||||
| ir.cpp:1777:17:1777:17 | Right | r1777_4 |
|
||||
| ir.cpp:1780:9:1780:18 | Address | &:r1780_2 |
|
||||
| ir.cpp:1780:9:1780:18 | Condition | r1780_10 |
|
||||
| ir.cpp:1780:9:1780:18 | Phi | from 8:m1775_1 |
|
||||
| ir.cpp:1780:9:1780:18 | Phi | from 9:m1777_7 |
|
||||
| ir.cpp:1780:13:1780:14 | Address | &:r1780_6 |
|
||||
| ir.cpp:1780:13:1780:14 | Left | r1780_7 |
|
||||
| ir.cpp:1780:13:1780:14 | Load | m1780_5 |
|
||||
| ir.cpp:1780:13:1780:14 | Right | r1780_8 |
|
||||
| ir.cpp:1780:13:1780:14 | Unary | r1780_9 |
|
||||
| ir.cpp:1780:18:1780:18 | Address | &:r1780_3 |
|
||||
| ir.cpp:1780:18:1780:18 | Load | m1775_5 |
|
||||
| ir.cpp:1780:18:1780:18 | StoreValue | r1780_4 |
|
||||
| ir.cpp:1781:9:1781:9 | Address | &:r1781_3 |
|
||||
| ir.cpp:1781:9:1781:9 | Address | &:r1781_3 |
|
||||
| ir.cpp:1781:9:1781:9 | Left | r1781_4 |
|
||||
| ir.cpp:1781:9:1781:9 | Load | m1780_1 |
|
||||
| ir.cpp:1781:9:1781:15 | StoreValue | r1781_5 |
|
||||
| ir.cpp:1781:14:1781:15 | Address | &:r1781_1 |
|
||||
| ir.cpp:1781:14:1781:15 | Load | m1780_5 |
|
||||
| ir.cpp:1781:14:1781:15 | Right | r1781_2 |
|
||||
| ir.cpp:1785:6:1785:26 | ChiPartial | partial:m1785_3 |
|
||||
| ir.cpp:1785:6:1785:26 | ChiTotal | total:m1785_2 |
|
||||
| ir.cpp:1785:6:1785:26 | SideEffect | m1785_3 |
|
||||
| ir.cpp:1785:32:1785:32 | Address | &:r1785_5 |
|
||||
| ir.cpp:1786:17:1786:17 | Address | &:r1786_1 |
|
||||
| ir.cpp:1786:21:1786:21 | Address | &:r1786_2 |
|
||||
| ir.cpp:1786:21:1786:21 | Load | m1785_6 |
|
||||
| ir.cpp:1786:21:1786:21 | StoreValue | r1786_3 |
|
||||
| ir.cpp:1786:24:1786:24 | Address | &:r1786_5 |
|
||||
| ir.cpp:1786:24:1786:24 | Left | r1786_6 |
|
||||
| ir.cpp:1786:24:1786:24 | Load | m1785_6 |
|
||||
| ir.cpp:1786:24:1786:28 | Condition | r1786_8 |
|
||||
| ir.cpp:1786:28:1786:28 | Right | r1786_7 |
|
||||
| ir.cpp:1788:9:1788:9 | Address | &:r1788_6 |
|
||||
| ir.cpp:1788:13:1788:13 | Address | &:r1788_1 |
|
||||
| ir.cpp:1788:13:1788:13 | Left | r1788_2 |
|
||||
| ir.cpp:1788:13:1788:13 | Load | m1785_6 |
|
||||
| ir.cpp:1788:13:1788:17 | StoreValue | r1788_5 |
|
||||
| ir.cpp:1788:17:1788:17 | Address | &:r1788_3 |
|
||||
| ir.cpp:1788:17:1788:17 | Load | m1786_4 |
|
||||
| ir.cpp:1788:17:1788:17 | Right | r1788_4 |
|
||||
| ir.cpp:1791:9:1791:9 | Address | &:r1791_1 |
|
||||
| ir.cpp:1792:13:1792:13 | Address | &:r1792_3 |
|
||||
| ir.cpp:1792:17:1792:17 | Address | &:r1792_1 |
|
||||
| ir.cpp:1792:17:1792:17 | Load | m1788_7 |
|
||||
| ir.cpp:1792:17:1792:17 | StoreValue | r1792_2 |
|
||||
| ir.cpp:1792:20:1792:20 | Address | &:r1792_5 |
|
||||
| ir.cpp:1792:20:1792:20 | Left | r1792_6 |
|
||||
| ir.cpp:1792:20:1792:20 | Load | m1788_7 |
|
||||
| ir.cpp:1792:20:1792:24 | Condition | r1792_8 |
|
||||
| ir.cpp:1792:24:1792:24 | Right | r1792_7 |
|
||||
| ir.cpp:1794:9:1794:9 | Address | &:r1794_6 |
|
||||
| ir.cpp:1794:13:1794:13 | Address | &:r1794_1 |
|
||||
| ir.cpp:1794:13:1794:13 | Left | r1794_2 |
|
||||
| ir.cpp:1794:13:1794:13 | Load | m1788_7 |
|
||||
| ir.cpp:1794:13:1794:17 | StoreValue | r1794_5 |
|
||||
| ir.cpp:1794:17:1794:17 | Address | &:r1794_3 |
|
||||
| ir.cpp:1794:17:1794:17 | Load | m1792_4 |
|
||||
| ir.cpp:1794:17:1794:17 | Right | r1794_4 |
|
||||
| ir.cpp:1797:13:1797:13 | Address | &:r1797_3 |
|
||||
| ir.cpp:1797:17:1797:17 | Address | &:r1797_1 |
|
||||
| ir.cpp:1797:17:1797:17 | Load | m1794_7 |
|
||||
| ir.cpp:1797:17:1797:17 | StoreValue | r1797_2 |
|
||||
| ir.cpp:1797:18:1797:29 | Address | &:r1797_5 |
|
||||
| ir.cpp:1797:18:1797:29 | Condition | r1797_11 |
|
||||
| ir.cpp:1797:24:1797:25 | Address | &:r1797_9 |
|
||||
| ir.cpp:1797:24:1797:25 | Load | m1797_8 |
|
||||
| ir.cpp:1797:24:1797:25 | Unary | r1797_10 |
|
||||
| ir.cpp:1797:29:1797:29 | Address | &:r1797_6 |
|
||||
| ir.cpp:1797:29:1797:29 | Load | m1797_4 |
|
||||
| ir.cpp:1797:29:1797:29 | StoreValue | r1797_7 |
|
||||
| ir.cpp:1799:9:1799:9 | Address | &:r1799_6 |
|
||||
| ir.cpp:1799:13:1799:13 | Address | &:r1799_1 |
|
||||
| ir.cpp:1799:13:1799:13 | Left | r1799_2 |
|
||||
| ir.cpp:1799:13:1799:13 | Load | m1794_7 |
|
||||
| ir.cpp:1799:13:1799:17 | StoreValue | r1799_5 |
|
||||
| ir.cpp:1799:17:1799:17 | Address | &:r1799_3 |
|
||||
| ir.cpp:1799:17:1799:17 | Load | m1797_4 |
|
||||
| ir.cpp:1799:17:1799:17 | Right | r1799_4 |
|
||||
| ir.cpp:1802:13:1802:33 | Address | &:r1802_5 |
|
||||
| ir.cpp:1802:13:1802:33 | Condition | r1802_11 |
|
||||
| ir.cpp:1802:17:1802:17 | Address | &:r1802_1 |
|
||||
| ir.cpp:1802:21:1802:21 | Address | &:r1802_2 |
|
||||
| ir.cpp:1802:21:1802:21 | Load | m1799_7 |
|
||||
| ir.cpp:1802:21:1802:21 | StoreValue | r1802_3 |
|
||||
| ir.cpp:1802:28:1802:29 | Address | &:r1802_9 |
|
||||
| ir.cpp:1802:28:1802:29 | Load | m1802_8 |
|
||||
| ir.cpp:1802:28:1802:29 | Unary | r1802_10 |
|
||||
| ir.cpp:1802:33:1802:33 | Address | &:r1802_6 |
|
||||
| ir.cpp:1802:33:1802:33 | Load | m1802_4 |
|
||||
| ir.cpp:1802:33:1802:33 | StoreValue | r1802_7 |
|
||||
| ir.cpp:1804:9:1804:9 | Address | &:r1804_6 |
|
||||
| ir.cpp:1804:13:1804:13 | Address | &:r1804_1 |
|
||||
| ir.cpp:1804:13:1804:13 | Left | r1804_2 |
|
||||
| ir.cpp:1804:13:1804:13 | Load | m1799_7 |
|
||||
| ir.cpp:1804:13:1804:17 | StoreValue | r1804_5 |
|
||||
| ir.cpp:1804:17:1804:17 | Address | &:r1804_3 |
|
||||
| ir.cpp:1804:17:1804:17 | Load | m1802_4 |
|
||||
| ir.cpp:1804:17:1804:17 | Right | r1804_4 |
|
||||
| ir.cpp:1807:9:1807:9 | Address | &:r1807_1 |
|
||||
| ir.cpp:1807:13:1807:13 | Address | &:r1807_2 |
|
||||
| ir.cpp:1807:13:1807:13 | Load | m1804_7 |
|
||||
| ir.cpp:1807:13:1807:13 | StoreValue | r1807_3 |
|
||||
| ir.cpp:1808:13:1808:13 | Address | &:r1808_1 |
|
||||
| ir.cpp:1808:13:1808:13 | Condition | r1808_2 |
|
||||
| ir.cpp:1808:13:1808:13 | Load | m1807_4 |
|
||||
| ir.cpp:1810:9:1810:9 | Address | &:r1810_6 |
|
||||
| ir.cpp:1810:13:1810:13 | Address | &:r1810_1 |
|
||||
| ir.cpp:1810:13:1810:13 | Left | r1810_2 |
|
||||
| ir.cpp:1810:13:1810:13 | Load | m1804_7 |
|
||||
| ir.cpp:1810:13:1810:17 | StoreValue | r1810_5 |
|
||||
| ir.cpp:1810:17:1810:17 | Address | &:r1810_3 |
|
||||
| ir.cpp:1810:17:1810:17 | Load | m1807_4 |
|
||||
| ir.cpp:1810:17:1810:17 | Right | r1810_4 |
|
||||
| ir.cpp:1813:13:1813:22 | Address | &:r1813_1 |
|
||||
| ir.cpp:1813:13:1813:22 | Condition | r1813_7 |
|
||||
| ir.cpp:1813:17:1813:18 | Address | &:r1813_5 |
|
||||
| ir.cpp:1813:17:1813:18 | Load | m1813_4 |
|
||||
| ir.cpp:1813:17:1813:18 | Unary | r1813_6 |
|
||||
| ir.cpp:1813:22:1813:22 | Address | &:r1813_2 |
|
||||
| ir.cpp:1813:22:1813:22 | Load | m1807_4 |
|
||||
| ir.cpp:1813:22:1813:22 | StoreValue | r1813_3 |
|
||||
| ir.cpp:1815:9:1815:9 | Address | &:r1815_3 |
|
||||
| ir.cpp:1815:9:1815:9 | Address | &:r1815_3 |
|
||||
| ir.cpp:1815:9:1815:9 | Left | r1815_4 |
|
||||
| ir.cpp:1815:9:1815:9 | Load | m1810_7 |
|
||||
| ir.cpp:1815:9:1815:15 | StoreValue | r1815_5 |
|
||||
| ir.cpp:1815:14:1815:15 | Address | &:r1815_1 |
|
||||
| ir.cpp:1815:14:1815:15 | Load | m1813_4 |
|
||||
| ir.cpp:1815:14:1815:15 | Right | r1815_2 |
|
||||
| perf-regression.cpp:6:3:6:5 | Address | &:r6_5 |
|
||||
| perf-regression.cpp:6:3:6:5 | Address | &:r6_5 |
|
||||
| perf-regression.cpp:6:3:6:5 | Address | &:r6_7 |
|
||||
|
||||
@@ -9418,6 +9418,308 @@ ir.cpp:
|
||||
# 1750| v1750_6(void) = AliasedUse : ~m?
|
||||
# 1750| v1750_7(void) = ExitFunction :
|
||||
|
||||
# 1757| void if_initialization(int)
|
||||
# 1757| Block 0
|
||||
# 1757| v1757_1(void) = EnterFunction :
|
||||
# 1757| mu1757_2(unknown) = AliasedDefinition :
|
||||
# 1757| mu1757_3(unknown) = InitializeNonLocal :
|
||||
# 1757| r1757_4(glval<int>) = VariableAddress[x] :
|
||||
# 1757| mu1757_5(int) = InitializeParameter[x] : &:r1757_4
|
||||
# 1758| r1758_1(glval<int>) = VariableAddress[y] :
|
||||
# 1758| r1758_2(glval<int>) = VariableAddress[x] :
|
||||
# 1758| r1758_3(int) = Load[x] : &:r1758_2, ~m?
|
||||
# 1758| mu1758_4(int) = Store[y] : &:r1758_1, r1758_3
|
||||
# 1758| r1758_5(glval<int>) = VariableAddress[x] :
|
||||
# 1758| r1758_6(int) = Load[x] : &:r1758_5, ~m?
|
||||
# 1758| r1758_7(int) = Constant[1] :
|
||||
# 1758| r1758_8(int) = Add : r1758_6, r1758_7
|
||||
# 1758| r1758_9(int) = Constant[0] :
|
||||
# 1758| r1758_10(bool) = CompareNE : r1758_8, r1758_9
|
||||
# 1758| v1758_11(void) = ConditionalBranch : r1758_10
|
||||
#-----| False -> Block 2
|
||||
#-----| True -> Block 1
|
||||
|
||||
# 1759| Block 1
|
||||
# 1759| r1759_1(glval<int>) = VariableAddress[x] :
|
||||
# 1759| r1759_2(int) = Load[x] : &:r1759_1, ~m?
|
||||
# 1759| r1759_3(glval<int>) = VariableAddress[y] :
|
||||
# 1759| r1759_4(int) = Load[y] : &:r1759_3, ~m?
|
||||
# 1759| r1759_5(int) = Add : r1759_2, r1759_4
|
||||
# 1759| r1759_6(glval<int>) = VariableAddress[x] :
|
||||
# 1759| mu1759_7(int) = Store[x] : &:r1759_6, r1759_5
|
||||
#-----| Goto -> Block 2
|
||||
|
||||
# 1762| Block 2
|
||||
# 1762| r1762_1(glval<int>) = VariableAddress[w] :
|
||||
# 1762| mu1762_2(int) = Uninitialized[w] : &:r1762_1
|
||||
# 1763| r1763_1(glval<int>) = VariableAddress[x] :
|
||||
# 1763| r1763_2(int) = Load[x] : &:r1763_1, ~m?
|
||||
# 1763| r1763_3(glval<int>) = VariableAddress[w] :
|
||||
# 1763| mu1763_4(int) = Store[w] : &:r1763_3, r1763_2
|
||||
# 1763| r1763_5(glval<int>) = VariableAddress[x] :
|
||||
# 1763| r1763_6(int) = Load[x] : &:r1763_5, ~m?
|
||||
# 1763| r1763_7(int) = Constant[1] :
|
||||
# 1763| r1763_8(int) = Add : r1763_6, r1763_7
|
||||
# 1763| r1763_9(int) = Constant[0] :
|
||||
# 1763| r1763_10(bool) = CompareNE : r1763_8, r1763_9
|
||||
# 1763| v1763_11(void) = ConditionalBranch : r1763_10
|
||||
#-----| False -> Block 4
|
||||
#-----| True -> Block 3
|
||||
|
||||
# 1764| Block 3
|
||||
# 1764| r1764_1(glval<int>) = VariableAddress[x] :
|
||||
# 1764| r1764_2(int) = Load[x] : &:r1764_1, ~m?
|
||||
# 1764| r1764_3(glval<int>) = VariableAddress[w] :
|
||||
# 1764| r1764_4(int) = Load[w] : &:r1764_3, ~m?
|
||||
# 1764| r1764_5(int) = Add : r1764_2, r1764_4
|
||||
# 1764| r1764_6(glval<int>) = VariableAddress[x] :
|
||||
# 1764| mu1764_7(int) = Store[x] : &:r1764_6, r1764_5
|
||||
#-----| Goto -> Block 4
|
||||
|
||||
# 1767| Block 4
|
||||
# 1767| r1767_1(glval<int>) = VariableAddress[x] :
|
||||
# 1767| r1767_2(int) = Load[x] : &:r1767_1, ~m?
|
||||
# 1767| r1767_3(glval<int>) = VariableAddress[w] :
|
||||
# 1767| mu1767_4(int) = Store[w] : &:r1767_3, r1767_2
|
||||
# 1767| r1767_5(glval<int>) = VariableAddress[w2] :
|
||||
# 1767| r1767_6(glval<int>) = VariableAddress[w] :
|
||||
# 1767| r1767_7(int) = Load[w] : &:r1767_6, ~m?
|
||||
# 1767| mu1767_8(int) = Store[w2] : &:r1767_5, r1767_7
|
||||
# 1767| r1767_9(glval<int>) = VariableAddress[w2] :
|
||||
# 1767| r1767_10(int) = Load[w2] : &:r1767_9, ~m?
|
||||
# 1767| r1767_11(int) = Constant[0] :
|
||||
# 1767| r1767_12(bool) = CompareNE : r1767_10, r1767_11
|
||||
# 1767| r1767_13(bool) = CopyValue : r1767_12
|
||||
# 1767| v1767_14(void) = ConditionalBranch : r1767_13
|
||||
#-----| False -> Block 6
|
||||
#-----| True -> Block 5
|
||||
|
||||
# 1768| Block 5
|
||||
# 1768| r1768_1(glval<int>) = VariableAddress[x] :
|
||||
# 1768| r1768_2(int) = Load[x] : &:r1768_1, ~m?
|
||||
# 1768| r1768_3(glval<int>) = VariableAddress[w] :
|
||||
# 1768| r1768_4(int) = Load[w] : &:r1768_3, ~m?
|
||||
# 1768| r1768_5(int) = Add : r1768_2, r1768_4
|
||||
# 1768| r1768_6(glval<int>) = VariableAddress[x] :
|
||||
# 1768| mu1768_7(int) = Store[x] : &:r1768_6, r1768_5
|
||||
#-----| Goto -> Block 6
|
||||
|
||||
# 1771| Block 6
|
||||
# 1771| r1771_1(glval<int>) = VariableAddress[v] :
|
||||
# 1771| r1771_2(glval<int>) = VariableAddress[x] :
|
||||
# 1771| r1771_3(int) = Load[x] : &:r1771_2, ~m?
|
||||
# 1771| mu1771_4(int) = Store[v] : &:r1771_1, r1771_3
|
||||
# 1771| r1771_5(glval<int>) = VariableAddress[v2] :
|
||||
# 1771| r1771_6(glval<int>) = VariableAddress[v] :
|
||||
# 1771| r1771_7(int) = Load[v] : &:r1771_6, ~m?
|
||||
# 1771| mu1771_8(int) = Store[v2] : &:r1771_5, r1771_7
|
||||
# 1771| r1771_9(glval<int>) = VariableAddress[v2] :
|
||||
# 1771| r1771_10(int) = Load[v2] : &:r1771_9, ~m?
|
||||
# 1771| r1771_11(int) = Constant[0] :
|
||||
# 1771| r1771_12(bool) = CompareNE : r1771_10, r1771_11
|
||||
# 1771| r1771_13(bool) = CopyValue : r1771_12
|
||||
# 1771| v1771_14(void) = ConditionalBranch : r1771_13
|
||||
#-----| False -> Block 8
|
||||
#-----| True -> Block 7
|
||||
|
||||
# 1772| Block 7
|
||||
# 1772| r1772_1(glval<int>) = VariableAddress[x] :
|
||||
# 1772| r1772_2(int) = Load[x] : &:r1772_1, ~m?
|
||||
# 1772| r1772_3(glval<int>) = VariableAddress[v] :
|
||||
# 1772| r1772_4(int) = Load[v] : &:r1772_3, ~m?
|
||||
# 1772| r1772_5(int) = Add : r1772_2, r1772_4
|
||||
# 1772| r1772_6(glval<int>) = VariableAddress[x] :
|
||||
# 1772| mu1772_7(int) = Store[x] : &:r1772_6, r1772_5
|
||||
#-----| Goto -> Block 8
|
||||
|
||||
# 1775| Block 8
|
||||
# 1775| r1775_1(glval<int>) = VariableAddress[z] :
|
||||
# 1775| r1775_2(glval<int>) = VariableAddress[x] :
|
||||
# 1775| r1775_3(int) = Load[x] : &:r1775_2, ~m?
|
||||
# 1775| mu1775_4(int) = Store[z] : &:r1775_1, r1775_3
|
||||
# 1776| r1776_1(glval<int>) = VariableAddress[z] :
|
||||
# 1776| r1776_2(int) = Load[z] : &:r1776_1, ~m?
|
||||
# 1776| r1776_3(int) = Constant[0] :
|
||||
# 1776| r1776_4(bool) = CompareNE : r1776_2, r1776_3
|
||||
# 1776| v1776_5(void) = ConditionalBranch : r1776_4
|
||||
#-----| False -> Block 10
|
||||
#-----| True -> Block 9
|
||||
|
||||
# 1777| Block 9
|
||||
# 1777| r1777_1(glval<int>) = VariableAddress[x] :
|
||||
# 1777| r1777_2(int) = Load[x] : &:r1777_1, ~m?
|
||||
# 1777| r1777_3(glval<int>) = VariableAddress[z] :
|
||||
# 1777| r1777_4(int) = Load[z] : &:r1777_3, ~m?
|
||||
# 1777| r1777_5(int) = Add : r1777_2, r1777_4
|
||||
# 1777| r1777_6(glval<int>) = VariableAddress[x] :
|
||||
# 1777| mu1777_7(int) = Store[x] : &:r1777_6, r1777_5
|
||||
#-----| Goto -> Block 10
|
||||
|
||||
# 1780| Block 10
|
||||
# 1780| r1780_1(glval<int>) = VariableAddress[z2] :
|
||||
# 1780| r1780_2(glval<int>) = VariableAddress[z] :
|
||||
# 1780| r1780_3(int) = Load[z] : &:r1780_2, ~m?
|
||||
# 1780| mu1780_4(int) = Store[z2] : &:r1780_1, r1780_3
|
||||
# 1780| r1780_5(glval<int>) = VariableAddress[z2] :
|
||||
# 1780| r1780_6(int) = Load[z2] : &:r1780_5, ~m?
|
||||
# 1780| r1780_7(int) = Constant[0] :
|
||||
# 1780| r1780_8(bool) = CompareNE : r1780_6, r1780_7
|
||||
# 1780| r1780_9(bool) = CopyValue : r1780_8
|
||||
# 1780| v1780_10(void) = ConditionalBranch : r1780_9
|
||||
#-----| False -> Block 12
|
||||
#-----| True -> Block 11
|
||||
|
||||
# 1781| Block 11
|
||||
# 1781| r1781_1(glval<int>) = VariableAddress[z2] :
|
||||
# 1781| r1781_2(int) = Load[z2] : &:r1781_1, ~m?
|
||||
# 1781| r1781_3(glval<int>) = VariableAddress[x] :
|
||||
# 1781| r1781_4(int) = Load[x] : &:r1781_3, ~m?
|
||||
# 1781| r1781_5(int) = Add : r1781_4, r1781_2
|
||||
# 1781| mu1781_6(int) = Store[x] : &:r1781_3, r1781_5
|
||||
#-----| Goto -> Block 12
|
||||
|
||||
# 1783| Block 12
|
||||
# 1783| v1783_1(void) = NoOp :
|
||||
# 1757| v1757_6(void) = ReturnVoid :
|
||||
# 1757| v1757_7(void) = AliasedUse : ~m?
|
||||
# 1757| v1757_8(void) = ExitFunction :
|
||||
|
||||
# 1785| void switch_initialization(int)
|
||||
# 1785| Block 0
|
||||
# 1785| v1785_1(void) = EnterFunction :
|
||||
# 1785| mu1785_2(unknown) = AliasedDefinition :
|
||||
# 1785| mu1785_3(unknown) = InitializeNonLocal :
|
||||
# 1785| r1785_4(glval<int>) = VariableAddress[x] :
|
||||
# 1785| mu1785_5(int) = InitializeParameter[x] : &:r1785_4
|
||||
# 1786| r1786_1(glval<int>) = VariableAddress[y] :
|
||||
# 1786| r1786_2(glval<int>) = VariableAddress[x] :
|
||||
# 1786| r1786_3(int) = Load[x] : &:r1786_2, ~m?
|
||||
# 1786| mu1786_4(int) = Store[y] : &:r1786_1, r1786_3
|
||||
# 1786| r1786_5(glval<int>) = VariableAddress[x] :
|
||||
# 1786| r1786_6(int) = Load[x] : &:r1786_5, ~m?
|
||||
# 1786| r1786_7(int) = Constant[1] :
|
||||
# 1786| r1786_8(int) = Add : r1786_6, r1786_7
|
||||
# 1786| v1786_9(void) = Switch : r1786_8
|
||||
#-----| Default -> Block 1
|
||||
|
||||
# 1787| Block 1
|
||||
# 1787| v1787_1(void) = NoOp :
|
||||
# 1788| r1788_1(glval<int>) = VariableAddress[x] :
|
||||
# 1788| r1788_2(int) = Load[x] : &:r1788_1, ~m?
|
||||
# 1788| r1788_3(glval<int>) = VariableAddress[y] :
|
||||
# 1788| r1788_4(int) = Load[y] : &:r1788_3, ~m?
|
||||
# 1788| r1788_5(int) = Add : r1788_2, r1788_4
|
||||
# 1788| r1788_6(glval<int>) = VariableAddress[x] :
|
||||
# 1788| mu1788_7(int) = Store[x] : &:r1788_6, r1788_5
|
||||
# 1791| r1791_1(glval<int>) = VariableAddress[w] :
|
||||
# 1791| mu1791_2(int) = Uninitialized[w] : &:r1791_1
|
||||
# 1792| r1792_1(glval<int>) = VariableAddress[x] :
|
||||
# 1792| r1792_2(int) = Load[x] : &:r1792_1, ~m?
|
||||
# 1792| r1792_3(glval<int>) = VariableAddress[w] :
|
||||
# 1792| mu1792_4(int) = Store[w] : &:r1792_3, r1792_2
|
||||
# 1792| r1792_5(glval<int>) = VariableAddress[x] :
|
||||
# 1792| r1792_6(int) = Load[x] : &:r1792_5, ~m?
|
||||
# 1792| r1792_7(int) = Constant[1] :
|
||||
# 1792| r1792_8(int) = Add : r1792_6, r1792_7
|
||||
# 1792| v1792_9(void) = Switch : r1792_8
|
||||
#-----| Default -> Block 2
|
||||
|
||||
# 1793| Block 2
|
||||
# 1793| v1793_1(void) = NoOp :
|
||||
# 1794| r1794_1(glval<int>) = VariableAddress[x] :
|
||||
# 1794| r1794_2(int) = Load[x] : &:r1794_1, ~m?
|
||||
# 1794| r1794_3(glval<int>) = VariableAddress[w] :
|
||||
# 1794| r1794_4(int) = Load[w] : &:r1794_3, ~m?
|
||||
# 1794| r1794_5(int) = Add : r1794_2, r1794_4
|
||||
# 1794| r1794_6(glval<int>) = VariableAddress[x] :
|
||||
# 1794| mu1794_7(int) = Store[x] : &:r1794_6, r1794_5
|
||||
# 1797| r1797_1(glval<int>) = VariableAddress[x] :
|
||||
# 1797| r1797_2(int) = Load[x] : &:r1797_1, ~m?
|
||||
# 1797| r1797_3(glval<int>) = VariableAddress[w] :
|
||||
# 1797| mu1797_4(int) = Store[w] : &:r1797_3, r1797_2
|
||||
# 1797| r1797_5(glval<int>) = VariableAddress[w2] :
|
||||
# 1797| r1797_6(glval<int>) = VariableAddress[w] :
|
||||
# 1797| r1797_7(int) = Load[w] : &:r1797_6, ~m?
|
||||
# 1797| mu1797_8(int) = Store[w2] : &:r1797_5, r1797_7
|
||||
# 1797| r1797_9(glval<int>) = VariableAddress[w2] :
|
||||
# 1797| r1797_10(int) = Load[w2] : &:r1797_9, ~m?
|
||||
# 1797| r1797_11(int) = CopyValue : r1797_10
|
||||
# 1797| v1797_12(void) = Switch : r1797_11
|
||||
#-----| Default -> Block 3
|
||||
|
||||
# 1798| Block 3
|
||||
# 1798| v1798_1(void) = NoOp :
|
||||
# 1799| r1799_1(glval<int>) = VariableAddress[x] :
|
||||
# 1799| r1799_2(int) = Load[x] : &:r1799_1, ~m?
|
||||
# 1799| r1799_3(glval<int>) = VariableAddress[w] :
|
||||
# 1799| r1799_4(int) = Load[w] : &:r1799_3, ~m?
|
||||
# 1799| r1799_5(int) = Add : r1799_2, r1799_4
|
||||
# 1799| r1799_6(glval<int>) = VariableAddress[x] :
|
||||
# 1799| mu1799_7(int) = Store[x] : &:r1799_6, r1799_5
|
||||
# 1802| r1802_1(glval<int>) = VariableAddress[v] :
|
||||
# 1802| r1802_2(glval<int>) = VariableAddress[x] :
|
||||
# 1802| r1802_3(int) = Load[x] : &:r1802_2, ~m?
|
||||
# 1802| mu1802_4(int) = Store[v] : &:r1802_1, r1802_3
|
||||
# 1802| r1802_5(glval<int>) = VariableAddress[v2] :
|
||||
# 1802| r1802_6(glval<int>) = VariableAddress[v] :
|
||||
# 1802| r1802_7(int) = Load[v] : &:r1802_6, ~m?
|
||||
# 1802| mu1802_8(int) = Store[v2] : &:r1802_5, r1802_7
|
||||
# 1802| r1802_9(glval<int>) = VariableAddress[v2] :
|
||||
# 1802| r1802_10(int) = Load[v2] : &:r1802_9, ~m?
|
||||
# 1802| r1802_11(int) = CopyValue : r1802_10
|
||||
# 1802| v1802_12(void) = Switch : r1802_11
|
||||
#-----| Default -> Block 4
|
||||
|
||||
# 1803| Block 4
|
||||
# 1803| v1803_1(void) = NoOp :
|
||||
# 1804| r1804_1(glval<int>) = VariableAddress[x] :
|
||||
# 1804| r1804_2(int) = Load[x] : &:r1804_1, ~m?
|
||||
# 1804| r1804_3(glval<int>) = VariableAddress[v] :
|
||||
# 1804| r1804_4(int) = Load[v] : &:r1804_3, ~m?
|
||||
# 1804| r1804_5(int) = Add : r1804_2, r1804_4
|
||||
# 1804| r1804_6(glval<int>) = VariableAddress[x] :
|
||||
# 1804| mu1804_7(int) = Store[x] : &:r1804_6, r1804_5
|
||||
# 1807| r1807_1(glval<int>) = VariableAddress[z] :
|
||||
# 1807| r1807_2(glval<int>) = VariableAddress[x] :
|
||||
# 1807| r1807_3(int) = Load[x] : &:r1807_2, ~m?
|
||||
# 1807| mu1807_4(int) = Store[z] : &:r1807_1, r1807_3
|
||||
# 1808| r1808_1(glval<int>) = VariableAddress[z] :
|
||||
# 1808| r1808_2(int) = Load[z] : &:r1808_1, ~m?
|
||||
# 1808| v1808_3(void) = Switch : r1808_2
|
||||
#-----| Default -> Block 5
|
||||
|
||||
# 1809| Block 5
|
||||
# 1809| v1809_1(void) = NoOp :
|
||||
# 1810| r1810_1(glval<int>) = VariableAddress[x] :
|
||||
# 1810| r1810_2(int) = Load[x] : &:r1810_1, ~m?
|
||||
# 1810| r1810_3(glval<int>) = VariableAddress[z] :
|
||||
# 1810| r1810_4(int) = Load[z] : &:r1810_3, ~m?
|
||||
# 1810| r1810_5(int) = Add : r1810_2, r1810_4
|
||||
# 1810| r1810_6(glval<int>) = VariableAddress[x] :
|
||||
# 1810| mu1810_7(int) = Store[x] : &:r1810_6, r1810_5
|
||||
# 1813| r1813_1(glval<int>) = VariableAddress[z2] :
|
||||
# 1813| r1813_2(glval<int>) = VariableAddress[z] :
|
||||
# 1813| r1813_3(int) = Load[z] : &:r1813_2, ~m?
|
||||
# 1813| mu1813_4(int) = Store[z2] : &:r1813_1, r1813_3
|
||||
# 1813| r1813_5(glval<int>) = VariableAddress[z2] :
|
||||
# 1813| r1813_6(int) = Load[z2] : &:r1813_5, ~m?
|
||||
# 1813| r1813_7(int) = CopyValue : r1813_6
|
||||
# 1813| v1813_8(void) = Switch : r1813_7
|
||||
#-----| Default -> Block 6
|
||||
|
||||
# 1814| Block 6
|
||||
# 1814| v1814_1(void) = NoOp :
|
||||
# 1815| r1815_1(glval<int>) = VariableAddress[z2] :
|
||||
# 1815| r1815_2(int) = Load[z2] : &:r1815_1, ~m?
|
||||
# 1815| r1815_3(glval<int>) = VariableAddress[x] :
|
||||
# 1815| r1815_4(int) = Load[x] : &:r1815_3, ~m?
|
||||
# 1815| r1815_5(int) = Add : r1815_4, r1815_2
|
||||
# 1815| mu1815_6(int) = Store[x] : &:r1815_3, r1815_5
|
||||
# 1817| v1817_1(void) = NoOp :
|
||||
# 1785| v1785_6(void) = ReturnVoid :
|
||||
# 1785| v1785_7(void) = AliasedUse : ~m?
|
||||
# 1785| v1785_8(void) = ExitFunction :
|
||||
|
||||
perf-regression.cpp:
|
||||
# 6| void Big::Big()
|
||||
# 6| Block 0
|
||||
|
||||
8
cpp/ql/test/successor-tests/ifstmt/ifstmt/ifstmt.cpp
Normal file
8
cpp/ql/test/successor-tests/ifstmt/ifstmt/ifstmt.cpp
Normal file
@@ -0,0 +1,8 @@
|
||||
void normal(int x, int y) {
|
||||
if(int z = y; x == z) {
|
||||
l1:;
|
||||
}
|
||||
l2:;
|
||||
}
|
||||
|
||||
// semmle-extractor-options: -std=c++17
|
||||
@@ -1 +1,2 @@
|
||||
| ifstmt.c:28:6:28:11 | ... == ... | l2 |
|
||||
| ifstmt.cpp:2:17:2:22 | ... == ... | l2 |
|
||||
|
||||
@@ -1 +1,2 @@
|
||||
| ifstmt.c:28:6:28:11 | ... == ... | l1 |
|
||||
| ifstmt.cpp:2:17:2:22 | ... == ... | l1 |
|
||||
|
||||
@@ -1 +1,2 @@
|
||||
| ifstmt.c:29:8:29:8 | ; | l2 |
|
||||
| ifstmt.cpp:3:8:3:8 | ; | l2 |
|
||||
|
||||
@@ -1,6 +1,9 @@
|
||||
/**
|
||||
* @name ifstmt05
|
||||
* @description Every if statement has its condition or one of the condition's descendants as its unique successor.
|
||||
* @description Every if statement with an initialization has the initialization or one of the
|
||||
* initialization's descendants as its unique successor. Every if statement without
|
||||
* and initialization has its condition or one of the condition's descendants as
|
||||
* its unique successor.
|
||||
*/
|
||||
|
||||
import cpp
|
||||
@@ -8,7 +11,11 @@ import cpp
|
||||
from IfStmt is
|
||||
where
|
||||
not (
|
||||
is.getASuccessor() = is.getCondition().getAChild*() and
|
||||
(
|
||||
if exists(is.getInitialization())
|
||||
then is.getASuccessor() = is.getInitialization().getAChild*()
|
||||
else is.getASuccessor() = is.getCondition().getAChild*()
|
||||
) and
|
||||
count(is.getASuccessor()) = 1
|
||||
)
|
||||
select is
|
||||
|
||||
@@ -1,12 +1,27 @@
|
||||
| 0 | ifstmt.c:27:27:32:1 | { ... } | 1 | ifstmt.c:28:3:30:3 | if (...) ... |
|
||||
| 0 | ifstmt.cpp:1:27:6:1 | { ... } | 1 | ifstmt.cpp:2:3:4:3 | if (...) ... |
|
||||
| 1 | ifstmt.c:28:3:30:3 | if (...) ... | 1 | ifstmt.c:28:6:28:6 | x |
|
||||
| 1 | ifstmt.c:28:6:28:6 | x | 1 | ifstmt.c:28:11:28:11 | y |
|
||||
| 1 | ifstmt.c:28:6:28:11 | ... == ... | 1 | ifstmt.c:28:14:30:3 | { ... } |
|
||||
| 1 | ifstmt.c:28:6:28:11 | ... == ... | 4 | ifstmt.c:31:3:31:5 | label ...: |
|
||||
| 1 | ifstmt.c:28:11:28:11 | y | 1 | ifstmt.c:28:6:28:11 | ... == ... |
|
||||
| 1 | ifstmt.c:28:14:30:3 | { ... } | 2 | ifstmt.c:29:5:29:7 | label ...: |
|
||||
| 1 | ifstmt.cpp:2:3:4:3 | if (...) ... | 1 | ifstmt.cpp:2:6:2:6 | declaration |
|
||||
| 1 | ifstmt.cpp:2:6:2:6 | declaration | 1 | ifstmt.cpp:2:13:2:14 | initializer for z |
|
||||
| 1 | ifstmt.cpp:2:13:2:14 | initializer for z | 1 | ifstmt.cpp:2:14:2:14 | y |
|
||||
| 1 | ifstmt.cpp:2:14:2:14 | y | 1 | ifstmt.cpp:2:17:2:17 | x |
|
||||
| 1 | ifstmt.cpp:2:17:2:17 | x | 1 | ifstmt.cpp:2:22:2:22 | z |
|
||||
| 1 | ifstmt.cpp:2:17:2:22 | ... == ... | 1 | ifstmt.cpp:2:25:4:3 | { ... } |
|
||||
| 1 | ifstmt.cpp:2:17:2:22 | ... == ... | 4 | ifstmt.cpp:5:3:5:5 | label ...: |
|
||||
| 1 | ifstmt.cpp:2:22:2:22 | z | 1 | ifstmt.cpp:2:17:2:22 | ... == ... |
|
||||
| 1 | ifstmt.cpp:2:25:4:3 | { ... } | 2 | ifstmt.cpp:3:5:3:7 | label ...: |
|
||||
| 2 | ifstmt.c:29:5:29:7 | label ...: | 2 | ifstmt.c:29:8:29:8 | ; |
|
||||
| 2 | ifstmt.c:29:8:29:8 | ; | 4 | ifstmt.c:31:3:31:5 | label ...: |
|
||||
| 2 | ifstmt.cpp:3:5:3:7 | label ...: | 2 | ifstmt.cpp:3:8:3:8 | ; |
|
||||
| 2 | ifstmt.cpp:3:8:3:8 | ; | 4 | ifstmt.cpp:5:3:5:5 | label ...: |
|
||||
| 4 | ifstmt.c:31:3:31:5 | label ...: | 4 | ifstmt.c:31:6:31:6 | ; |
|
||||
| 4 | ifstmt.c:31:6:31:6 | ; | 5 | ifstmt.c:32:1:32:1 | return ... |
|
||||
| 4 | ifstmt.cpp:5:3:5:5 | label ...: | 4 | ifstmt.cpp:5:6:5:6 | ; |
|
||||
| 4 | ifstmt.cpp:5:6:5:6 | ; | 5 | ifstmt.cpp:6:1:6:1 | return ... |
|
||||
| 5 | ifstmt.c:32:1:32:1 | return ... | 0 | ifstmt.c:27:6:27:11 | normal |
|
||||
| 5 | ifstmt.cpp:6:1:6:1 | return ... | 0 | ifstmt.cpp:1:6:1:11 | normal |
|
||||
|
||||
15
cpp/ql/test/successor-tests/ifstmt/ifstmt/ifstmt11.ql
Normal file
15
cpp/ql/test/successor-tests/ifstmt/ifstmt/ifstmt11.ql
Normal file
@@ -0,0 +1,15 @@
|
||||
/**
|
||||
* @name ifstmt11
|
||||
* @description If an initialization exists, then the condition is a successor of the initialization.
|
||||
*/
|
||||
|
||||
import cpp
|
||||
|
||||
from IfStmt is, Expr e, Stmt s, ControlFlowNode n
|
||||
where
|
||||
s = is.getInitialization() and
|
||||
e = is.getCondition() and
|
||||
n = s.getASuccessor*() and
|
||||
not exists(ControlFlowNode m | m = e.getASuccessor*() | m = n) and
|
||||
not exists(ControlFlowNode m | m = e.getAPredecessor*() | m = n)
|
||||
select is
|
||||
@@ -12,3 +12,20 @@
|
||||
| switchstmt | switchstmt.c:1:6:1:6 | f | 7 | 8 | switchstmt.c:7:5:7:5 | switchstmt.c:7:5:7:5 | switchstmt.c:7:5:7:5 | ; | 8: return ... |
|
||||
| switchstmt | switchstmt.c:1:6:1:6 | f | 8 | 9 | switchstmt.c:8:1:8:1 | switchstmt.c:8:1:8:1 | switchstmt.c:8:1:8:1 | return ... | 8: f |
|
||||
| switchstmt | switchstmt.c:1:6:1:6 | f | 8 | 10 | switchstmt.c:1:6:1:6 | switchstmt.c:1:6:1:6 | switchstmt.c:1:6:1:6 | f | <none> |
|
||||
| switchstmt | switchstmt.cpp:3:6:3:6 | g | 3 | 1 | switchstmt.cpp:3:15:12:1 | switchstmt.cpp:3:15:12:1 | switchstmt.cpp:3:15:12:1 | { ... } | 4: switch (...) ... |
|
||||
| switchstmt | switchstmt.cpp:3:6:3:6 | g | 4 | 2 | switchstmt.cpp:4:6:10:5 | switchstmt.cpp:4:6:10:5 | switchstmt.cpp:4:6:10:5 | switch (...) ... | 5: declaration |
|
||||
| switchstmt | switchstmt.cpp:3:6:3:6 | g | 5 | 3 | switchstmt.cpp:5:10:5:10 | switchstmt.cpp:5:10:5:10 | switchstmt.cpp:5:10:5:10 | declaration | 5: initializer for y |
|
||||
| switchstmt | switchstmt.cpp:3:6:3:6 | g | 5 | 4 | switchstmt.cpp:5:17:5:18 | switchstmt.cpp:5:17:5:18 | switchstmt.cpp:5:17:5:18 | initializer for y | 5: x |
|
||||
| switchstmt | switchstmt.cpp:3:6:3:6 | g | 5 | 5 | switchstmt.cpp:5:18:5:18 | switchstmt.cpp:5:18:5:18 | switchstmt.cpp:5:18:5:18 | x | 6: y |
|
||||
| switchstmt | switchstmt.cpp:3:6:3:6 | g | 6 | 6 | switchstmt.cpp:6:10:6:10 | switchstmt.cpp:6:10:6:10 | switchstmt.cpp:6:10:6:10 | y | 6: { ... } |
|
||||
| switchstmt | switchstmt.cpp:3:6:3:6 | g | 6 | 7 | switchstmt.cpp:6:13:10:5 | switchstmt.cpp:6:13:10:5 | switchstmt.cpp:6:13:10:5 | { ... } | 7: case ...: |
|
||||
| switchstmt | switchstmt.cpp:3:6:3:6 | g | 6 | 7 | switchstmt.cpp:6:13:10:5 | switchstmt.cpp:6:13:10:5 | switchstmt.cpp:6:13:10:5 | { ... } | 8: case ...: |
|
||||
| switchstmt | switchstmt.cpp:3:6:3:6 | g | 6 | 7 | switchstmt.cpp:6:13:10:5 | switchstmt.cpp:6:13:10:5 | switchstmt.cpp:6:13:10:5 | { ... } | 9: default: |
|
||||
| switchstmt | switchstmt.cpp:3:6:3:6 | g | 7 | 1 | switchstmt.cpp:7:14:7:14 | switchstmt.cpp:7:14:7:14 | switchstmt.cpp:7:14:7:14 | 1 | <none> |
|
||||
| switchstmt | switchstmt.cpp:3:6:3:6 | g | 7 | 8 | switchstmt.cpp:7:9:7:15 | switchstmt.cpp:7:9:7:15 | switchstmt.cpp:7:9:7:15 | case ...: | 8: case ...: |
|
||||
| switchstmt | switchstmt.cpp:3:6:3:6 | g | 8 | 1 | switchstmt.cpp:8:14:8:14 | switchstmt.cpp:8:14:8:14 | switchstmt.cpp:8:14:8:14 | 2 | <none> |
|
||||
| switchstmt | switchstmt.cpp:3:6:3:6 | g | 8 | 9 | switchstmt.cpp:8:9:8:15 | switchstmt.cpp:8:9:8:15 | switchstmt.cpp:8:9:8:15 | case ...: | 9: default: |
|
||||
| switchstmt | switchstmt.cpp:3:6:3:6 | g | 9 | 10 | switchstmt.cpp:9:9:9:16 | switchstmt.cpp:9:9:9:16 | switchstmt.cpp:9:9:9:16 | default: | 11: ; |
|
||||
| switchstmt | switchstmt.cpp:3:6:3:6 | g | 11 | 11 | switchstmt.cpp:11:5:11:5 | switchstmt.cpp:11:5:11:5 | switchstmt.cpp:11:5:11:5 | ; | 12: return ... |
|
||||
| switchstmt | switchstmt.cpp:3:6:3:6 | g | 12 | 12 | switchstmt.cpp:12:1:12:1 | switchstmt.cpp:12:1:12:1 | switchstmt.cpp:12:1:12:1 | return ... | 12: g |
|
||||
| switchstmt | switchstmt.cpp:3:6:3:6 | g | 12 | 13 | switchstmt.cpp:3:6:3:6 | switchstmt.cpp:3:6:3:6 | switchstmt.cpp:3:6:3:6 | g | <none> |
|
||||
|
||||
@@ -0,0 +1,12 @@
|
||||
// semmle-extractor-options: -std=c++17
|
||||
|
||||
void g(int x) {
|
||||
switch (
|
||||
int y = x;
|
||||
y) {
|
||||
case 1:
|
||||
case 2:
|
||||
default:
|
||||
}
|
||||
;
|
||||
}
|
||||
Reference in New Issue
Block a user