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C++: Handle C++17 switch initializers
This commit is contained in:
Jeroen Ketema
@@ -13776,6 +13776,205 @@ ir.cpp:
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# 1781| Type = [IntType] int
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# 1781| ValueCategory = prvalue(load)
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# 1783| getStmt(8): [ReturnStmt] return ...
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# 1785| [TopLevelFunction] void switch_initialization(int)
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# 1785| <params>:
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# 1785| getParameter(0): [Parameter] x
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# 1785| Type = [IntType] int
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# 1785| getEntryPoint(): [BlockStmt] { ... }
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# 1786| getStmt(0): [SwitchStmt] switch (...) ...
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# 1786| getInitialization(): [DeclStmt] declaration
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# 1786| getDeclarationEntry(0): [VariableDeclarationEntry] definition of y
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# 1786| Type = [IntType] int
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# 1786| getVariable().getInitializer(): [Initializer] initializer for y
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# 1786| getExpr(): [VariableAccess] x
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# 1786| Type = [IntType] int
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# 1786| ValueCategory = prvalue(load)
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# 1786| getExpr(): [AddExpr] ... + ...
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# 1786| Type = [IntType] int
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# 1786| ValueCategory = prvalue
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# 1786| getLeftOperand(): [VariableAccess] x
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# 1786| Type = [IntType] int
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# 1786| ValueCategory = prvalue(load)
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# 1786| getRightOperand(): [Literal] 1
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# 1786| Type = [IntType] int
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# 1786| Value = [Literal] 1
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# 1786| ValueCategory = prvalue
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# 1786| getStmt(): [BlockStmt] { ... }
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# 1787| getStmt(0): [SwitchCase] default:
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# 1788| getStmt(1): [ExprStmt] ExprStmt
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# 1788| getExpr(): [AssignExpr] ... = ...
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# 1788| Type = [IntType] int
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# 1788| ValueCategory = lvalue
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# 1788| getLValue(): [VariableAccess] x
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# 1788| Type = [IntType] int
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# 1788| ValueCategory = lvalue
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# 1788| getRValue(): [AddExpr] ... + ...
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# 1788| Type = [IntType] int
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# 1788| ValueCategory = prvalue
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# 1788| getLeftOperand(): [VariableAccess] x
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# 1788| Type = [IntType] int
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# 1788| ValueCategory = prvalue(load)
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# 1788| getRightOperand(): [VariableAccess] y
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# 1788| Type = [IntType] int
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# 1788| ValueCategory = prvalue(load)
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# 1791| getStmt(1): [DeclStmt] declaration
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# 1791| getDeclarationEntry(0): [VariableDeclarationEntry] definition of w
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# 1791| Type = [IntType] int
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# 1792| getStmt(2): [SwitchStmt] switch (...) ...
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# 1792| getInitialization(): [ExprStmt] ExprStmt
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# 1792| getExpr(): [AssignExpr] ... = ...
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# 1792| Type = [IntType] int
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# 1792| ValueCategory = lvalue
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# 1792| getLValue(): [VariableAccess] w
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# 1792| Type = [IntType] int
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# 1792| ValueCategory = lvalue
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# 1792| getRValue(): [VariableAccess] x
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# 1792| Type = [IntType] int
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# 1792| ValueCategory = prvalue(load)
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# 1792| getExpr(): [AddExpr] ... + ...
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# 1792| Type = [IntType] int
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# 1792| ValueCategory = prvalue
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# 1792| getLeftOperand(): [VariableAccess] x
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# 1792| Type = [IntType] int
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# 1792| ValueCategory = prvalue(load)
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# 1792| getRightOperand(): [Literal] 1
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# 1792| Type = [IntType] int
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# 1792| Value = [Literal] 1
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# 1792| ValueCategory = prvalue
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# 1792| getStmt(): [BlockStmt] { ... }
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# 1793| getStmt(0): [SwitchCase] default:
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# 1794| getStmt(1): [ExprStmt] ExprStmt
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# 1794| getExpr(): [AssignExpr] ... = ...
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# 1794| Type = [IntType] int
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# 1794| ValueCategory = lvalue
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# 1794| getLValue(): [VariableAccess] x
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# 1794| Type = [IntType] int
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# 1794| ValueCategory = lvalue
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# 1794| getRValue(): [AddExpr] ... + ...
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# 1794| Type = [IntType] int
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# 1794| ValueCategory = prvalue
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# 1794| getLeftOperand(): [VariableAccess] x
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# 1794| Type = [IntType] int
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# 1794| ValueCategory = prvalue(load)
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# 1794| getRightOperand(): [VariableAccess] w
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# 1794| Type = [IntType] int
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# 1794| ValueCategory = prvalue(load)
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# 1797| getStmt(3): [SwitchStmt] switch (...) ...
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# 1797| getInitialization(): [ExprStmt] ExprStmt
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# 1797| getExpr(): [AssignExpr] ... = ...
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# 1797| Type = [IntType] int
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# 1797| ValueCategory = lvalue
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# 1797| getLValue(): [VariableAccess] w
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# 1797| Type = [IntType] int
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# 1797| ValueCategory = lvalue
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# 1797| getRValue(): [VariableAccess] x
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# 1797| Type = [IntType] int
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# 1797| ValueCategory = prvalue(load)
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# 1797| getExpr(): [ConditionDeclExpr] (condition decl)
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# 1797| Type = [IntType] int
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# 1797| ValueCategory = prvalue
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# 1797| getVariableAccess(): [VariableAccess] w2
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# 1797| Type = [IntType] int
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# 1797| ValueCategory = prvalue(load)
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# 1797| getStmt(): [BlockStmt] { ... }
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# 1798| getStmt(0): [SwitchCase] default:
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# 1799| getStmt(1): [ExprStmt] ExprStmt
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# 1799| getExpr(): [AssignExpr] ... = ...
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# 1799| Type = [IntType] int
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# 1799| ValueCategory = lvalue
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# 1799| getLValue(): [VariableAccess] x
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# 1799| Type = [IntType] int
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# 1799| ValueCategory = lvalue
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# 1799| getRValue(): [AddExpr] ... + ...
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# 1799| Type = [IntType] int
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# 1799| ValueCategory = prvalue
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# 1799| getLeftOperand(): [VariableAccess] x
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# 1799| Type = [IntType] int
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# 1799| ValueCategory = prvalue(load)
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# 1799| getRightOperand(): [VariableAccess] w
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# 1799| Type = [IntType] int
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# 1799| ValueCategory = prvalue(load)
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# 1802| getStmt(4): [SwitchStmt] switch (...) ...
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# 1802| getInitialization(): [DeclStmt] declaration
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# 1802| getDeclarationEntry(0): [VariableDeclarationEntry] definition of v
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# 1802| Type = [IntType] int
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# 1802| getVariable().getInitializer(): [Initializer] initializer for v
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# 1802| getExpr(): [VariableAccess] x
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# 1802| Type = [IntType] int
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# 1802| ValueCategory = prvalue(load)
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# 1802| getExpr(): [ConditionDeclExpr] (condition decl)
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# 1802| Type = [IntType] int
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# 1802| ValueCategory = prvalue
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# 1802| getVariableAccess(): [VariableAccess] v2
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# 1802| Type = [IntType] int
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# 1802| ValueCategory = prvalue(load)
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# 1802| getStmt(): [BlockStmt] { ... }
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# 1803| getStmt(0): [SwitchCase] default:
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# 1804| getStmt(1): [ExprStmt] ExprStmt
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# 1804| getExpr(): [AssignExpr] ... = ...
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# 1804| Type = [IntType] int
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# 1804| ValueCategory = lvalue
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# 1804| getLValue(): [VariableAccess] x
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# 1804| Type = [IntType] int
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# 1804| ValueCategory = lvalue
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# 1804| getRValue(): [AddExpr] ... + ...
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# 1804| Type = [IntType] int
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# 1804| ValueCategory = prvalue
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# 1804| getLeftOperand(): [VariableAccess] x
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# 1804| Type = [IntType] int
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# 1804| ValueCategory = prvalue(load)
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# 1804| getRightOperand(): [VariableAccess] v
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# 1804| Type = [IntType] int
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# 1804| ValueCategory = prvalue(load)
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# 1807| getStmt(5): [DeclStmt] declaration
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# 1807| getDeclarationEntry(0): [VariableDeclarationEntry] definition of z
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# 1807| Type = [IntType] int
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# 1807| getVariable().getInitializer(): [Initializer] initializer for z
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# 1807| getExpr(): [VariableAccess] x
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# 1807| Type = [IntType] int
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# 1807| ValueCategory = prvalue(load)
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# 1808| getStmt(6): [SwitchStmt] switch (...) ...
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# 1808| getExpr(): [VariableAccess] z
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# 1808| Type = [IntType] int
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# 1808| ValueCategory = prvalue(load)
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# 1808| getStmt(): [BlockStmt] { ... }
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# 1809| getStmt(0): [SwitchCase] default:
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# 1810| getStmt(1): [ExprStmt] ExprStmt
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# 1810| getExpr(): [AssignExpr] ... = ...
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# 1810| Type = [IntType] int
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# 1810| ValueCategory = lvalue
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# 1810| getLValue(): [VariableAccess] x
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# 1810| Type = [IntType] int
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# 1810| ValueCategory = lvalue
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# 1810| getRValue(): [AddExpr] ... + ...
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# 1810| Type = [IntType] int
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# 1810| ValueCategory = prvalue
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# 1810| getLeftOperand(): [VariableAccess] x
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# 1810| Type = [IntType] int
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# 1810| ValueCategory = prvalue(load)
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# 1810| getRightOperand(): [VariableAccess] z
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# 1810| Type = [IntType] int
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# 1810| ValueCategory = prvalue(load)
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# 1813| getStmt(7): [SwitchStmt] switch (...) ...
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# 1813| getExpr(): [ConditionDeclExpr] (condition decl)
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# 1813| Type = [IntType] int
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# 1813| ValueCategory = prvalue
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# 1813| getVariableAccess(): [VariableAccess] z2
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# 1813| Type = [IntType] int
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# 1813| ValueCategory = prvalue(load)
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# 1813| getStmt(): [BlockStmt] { ... }
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# 1814| getStmt(0): [SwitchCase] default:
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# 1815| getStmt(1): [ExprStmt] ExprStmt
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# 1815| getExpr(): [AssignAddExpr] ... += ...
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# 1815| Type = [IntType] int
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# 1815| ValueCategory = lvalue
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# 1815| getLValue(): [VariableAccess] x
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# 1815| Type = [IntType] int
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# 1815| ValueCategory = lvalue
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# 1815| getRValue(): [VariableAccess] z2
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# 1815| Type = [IntType] int
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# 1815| ValueCategory = prvalue(load)
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# 1817| getStmt(8): [ReturnStmt] return ...
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perf-regression.cpp:
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# 4| [CopyAssignmentOperator] Big& Big::operator=(Big const&)
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# 4| <params>:
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@@ -1782,4 +1782,38 @@ void if_initialization(int x) {
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}
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}
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void switch_initialization(int x) {
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switch (int y = x; x + 1) {
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default:
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x = x + y;
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}
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int w;
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switch (w = x; x + 1) {
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default:
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x = x + w;
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}
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switch (w = x; int w2 = w) {
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default:
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x = x + w;
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}
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switch (int v = x; int v2 = v) {
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default:
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x = x + v;
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}
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int z = x;
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switch (z) {
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default:
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x = x + z;
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}
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switch (int z2 = z) {
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default:
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x += z2;
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}
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}
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// semmle-extractor-options: -std=c++17 --clang
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@@ -8347,6 +8347,116 @@
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| ir.cpp:1781:14:1781:15 | Address | &:r1781_1 |
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| ir.cpp:1781:14:1781:15 | Load | m1780_5 |
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| ir.cpp:1781:14:1781:15 | Right | r1781_2 |
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| ir.cpp:1785:6:1785:26 | ChiPartial | partial:m1785_3 |
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| ir.cpp:1785:6:1785:26 | ChiTotal | total:m1785_2 |
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| ir.cpp:1785:6:1785:26 | SideEffect | m1785_3 |
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| ir.cpp:1785:32:1785:32 | Address | &:r1785_5 |
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| ir.cpp:1786:17:1786:17 | Address | &:r1786_1 |
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| ir.cpp:1786:21:1786:21 | Address | &:r1786_2 |
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| ir.cpp:1786:21:1786:21 | Load | m1785_6 |
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| ir.cpp:1786:21:1786:21 | StoreValue | r1786_3 |
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| ir.cpp:1786:24:1786:24 | Address | &:r1786_5 |
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| ir.cpp:1786:24:1786:24 | Left | r1786_6 |
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| ir.cpp:1786:24:1786:24 | Load | m1785_6 |
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| ir.cpp:1786:24:1786:28 | Condition | r1786_8 |
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| ir.cpp:1786:28:1786:28 | Right | r1786_7 |
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| ir.cpp:1788:9:1788:9 | Address | &:r1788_6 |
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| ir.cpp:1788:13:1788:13 | Address | &:r1788_1 |
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| ir.cpp:1788:13:1788:13 | Left | r1788_2 |
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| ir.cpp:1788:13:1788:13 | Load | m1785_6 |
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| ir.cpp:1788:13:1788:17 | StoreValue | r1788_5 |
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| ir.cpp:1788:17:1788:17 | Address | &:r1788_3 |
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| ir.cpp:1788:17:1788:17 | Load | m1786_4 |
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| ir.cpp:1788:17:1788:17 | Right | r1788_4 |
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| ir.cpp:1791:9:1791:9 | Address | &:r1791_1 |
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| ir.cpp:1792:13:1792:13 | Address | &:r1792_3 |
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| ir.cpp:1792:17:1792:17 | Address | &:r1792_1 |
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| ir.cpp:1792:17:1792:17 | Load | m1788_7 |
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| ir.cpp:1792:17:1792:17 | StoreValue | r1792_2 |
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| ir.cpp:1792:20:1792:20 | Address | &:r1792_5 |
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| ir.cpp:1792:20:1792:20 | Left | r1792_6 |
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| ir.cpp:1792:20:1792:20 | Load | m1788_7 |
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| ir.cpp:1792:20:1792:24 | Condition | r1792_8 |
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| ir.cpp:1792:24:1792:24 | Right | r1792_7 |
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| ir.cpp:1794:9:1794:9 | Address | &:r1794_6 |
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| ir.cpp:1794:13:1794:13 | Address | &:r1794_1 |
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| ir.cpp:1794:13:1794:13 | Left | r1794_2 |
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| ir.cpp:1794:13:1794:13 | Load | m1788_7 |
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| ir.cpp:1794:13:1794:17 | StoreValue | r1794_5 |
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| ir.cpp:1794:17:1794:17 | Address | &:r1794_3 |
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| ir.cpp:1794:17:1794:17 | Load | m1792_4 |
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| ir.cpp:1794:17:1794:17 | Right | r1794_4 |
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| ir.cpp:1797:13:1797:13 | Address | &:r1797_3 |
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| ir.cpp:1797:17:1797:17 | Address | &:r1797_1 |
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| ir.cpp:1797:17:1797:17 | Load | m1794_7 |
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| ir.cpp:1797:17:1797:17 | StoreValue | r1797_2 |
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| ir.cpp:1797:18:1797:29 | Address | &:r1797_5 |
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| ir.cpp:1797:18:1797:29 | Condition | r1797_11 |
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| ir.cpp:1797:24:1797:25 | Address | &:r1797_9 |
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| ir.cpp:1797:24:1797:25 | Load | m1797_8 |
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| ir.cpp:1797:24:1797:25 | Unary | r1797_10 |
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| ir.cpp:1797:29:1797:29 | Address | &:r1797_6 |
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| ir.cpp:1797:29:1797:29 | Load | m1797_4 |
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| ir.cpp:1797:29:1797:29 | StoreValue | r1797_7 |
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| ir.cpp:1799:9:1799:9 | Address | &:r1799_6 |
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| ir.cpp:1799:13:1799:13 | Address | &:r1799_1 |
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| ir.cpp:1799:13:1799:13 | Left | r1799_2 |
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| ir.cpp:1799:13:1799:13 | Load | m1794_7 |
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| ir.cpp:1799:13:1799:17 | StoreValue | r1799_5 |
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| ir.cpp:1799:17:1799:17 | Address | &:r1799_3 |
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| ir.cpp:1799:17:1799:17 | Load | m1797_4 |
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| ir.cpp:1799:17:1799:17 | Right | r1799_4 |
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| ir.cpp:1802:13:1802:33 | Address | &:r1802_5 |
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| ir.cpp:1802:13:1802:33 | Condition | r1802_11 |
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| ir.cpp:1802:17:1802:17 | Address | &:r1802_1 |
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| ir.cpp:1802:21:1802:21 | Address | &:r1802_2 |
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| ir.cpp:1802:21:1802:21 | Load | m1799_7 |
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| ir.cpp:1802:21:1802:21 | StoreValue | r1802_3 |
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| ir.cpp:1802:28:1802:29 | Address | &:r1802_9 |
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| ir.cpp:1802:28:1802:29 | Load | m1802_8 |
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| ir.cpp:1802:28:1802:29 | Unary | r1802_10 |
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| ir.cpp:1802:33:1802:33 | Address | &:r1802_6 |
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| ir.cpp:1802:33:1802:33 | Load | m1802_4 |
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| ir.cpp:1802:33:1802:33 | StoreValue | r1802_7 |
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| ir.cpp:1804:9:1804:9 | Address | &:r1804_6 |
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| ir.cpp:1804:13:1804:13 | Address | &:r1804_1 |
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| ir.cpp:1804:13:1804:13 | Left | r1804_2 |
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| ir.cpp:1804:13:1804:13 | Load | m1799_7 |
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| ir.cpp:1804:13:1804:17 | StoreValue | r1804_5 |
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| ir.cpp:1804:17:1804:17 | Address | &:r1804_3 |
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| ir.cpp:1804:17:1804:17 | Load | m1802_4 |
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| ir.cpp:1804:17:1804:17 | Right | r1804_4 |
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| ir.cpp:1807:9:1807:9 | Address | &:r1807_1 |
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| ir.cpp:1807:13:1807:13 | Address | &:r1807_2 |
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| ir.cpp:1807:13:1807:13 | Load | m1804_7 |
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| ir.cpp:1807:13:1807:13 | StoreValue | r1807_3 |
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| ir.cpp:1808:13:1808:13 | Address | &:r1808_1 |
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| ir.cpp:1808:13:1808:13 | Condition | r1808_2 |
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| ir.cpp:1808:13:1808:13 | Load | m1807_4 |
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| ir.cpp:1810:9:1810:9 | Address | &:r1810_6 |
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| ir.cpp:1810:13:1810:13 | Address | &:r1810_1 |
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| ir.cpp:1810:13:1810:13 | Left | r1810_2 |
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| ir.cpp:1810:13:1810:13 | Load | m1804_7 |
|
||||
| ir.cpp:1810:13:1810:17 | StoreValue | r1810_5 |
|
||||
| ir.cpp:1810:17:1810:17 | Address | &:r1810_3 |
|
||||
| ir.cpp:1810:17:1810:17 | Load | m1807_4 |
|
||||
| ir.cpp:1810:17:1810:17 | Right | r1810_4 |
|
||||
| ir.cpp:1813:13:1813:22 | Address | &:r1813_1 |
|
||||
| ir.cpp:1813:13:1813:22 | Condition | r1813_7 |
|
||||
| ir.cpp:1813:17:1813:18 | Address | &:r1813_5 |
|
||||
| ir.cpp:1813:17:1813:18 | Load | m1813_4 |
|
||||
| ir.cpp:1813:17:1813:18 | Unary | r1813_6 |
|
||||
| ir.cpp:1813:22:1813:22 | Address | &:r1813_2 |
|
||||
| ir.cpp:1813:22:1813:22 | Load | m1807_4 |
|
||||
| ir.cpp:1813:22:1813:22 | StoreValue | r1813_3 |
|
||||
| ir.cpp:1815:9:1815:9 | Address | &:r1815_3 |
|
||||
| ir.cpp:1815:9:1815:9 | Address | &:r1815_3 |
|
||||
| ir.cpp:1815:9:1815:9 | Left | r1815_4 |
|
||||
| ir.cpp:1815:9:1815:9 | Load | m1810_7 |
|
||||
| ir.cpp:1815:9:1815:15 | StoreValue | r1815_5 |
|
||||
| ir.cpp:1815:14:1815:15 | Address | &:r1815_1 |
|
||||
| ir.cpp:1815:14:1815:15 | Load | m1813_4 |
|
||||
| ir.cpp:1815:14:1815:15 | Right | r1815_2 |
|
||||
| perf-regression.cpp:6:3:6:5 | Address | &:r6_5 |
|
||||
| perf-regression.cpp:6:3:6:5 | Address | &:r6_5 |
|
||||
| perf-regression.cpp:6:3:6:5 | Address | &:r6_7 |
|
||||
|
||||
@@ -9584,6 +9584,142 @@ ir.cpp:
|
||||
# 1757| v1757_7(void) = AliasedUse : ~m?
|
||||
# 1757| v1757_8(void) = ExitFunction :
|
||||
|
||||
# 1785| void switch_initialization(int)
|
||||
# 1785| Block 0
|
||||
# 1785| v1785_1(void) = EnterFunction :
|
||||
# 1785| mu1785_2(unknown) = AliasedDefinition :
|
||||
# 1785| mu1785_3(unknown) = InitializeNonLocal :
|
||||
# 1785| r1785_4(glval<int>) = VariableAddress[x] :
|
||||
# 1785| mu1785_5(int) = InitializeParameter[x] : &:r1785_4
|
||||
# 1786| r1786_1(glval<int>) = VariableAddress[y] :
|
||||
# 1786| r1786_2(glval<int>) = VariableAddress[x] :
|
||||
# 1786| r1786_3(int) = Load[x] : &:r1786_2, ~m?
|
||||
# 1786| mu1786_4(int) = Store[y] : &:r1786_1, r1786_3
|
||||
# 1786| r1786_5(glval<int>) = VariableAddress[x] :
|
||||
# 1786| r1786_6(int) = Load[x] : &:r1786_5, ~m?
|
||||
# 1786| r1786_7(int) = Constant[1] :
|
||||
# 1786| r1786_8(int) = Add : r1786_6, r1786_7
|
||||
# 1786| v1786_9(void) = Switch : r1786_8
|
||||
#-----| Default -> Block 1
|
||||
|
||||
# 1787| Block 1
|
||||
# 1787| v1787_1(void) = NoOp :
|
||||
# 1788| r1788_1(glval<int>) = VariableAddress[x] :
|
||||
# 1788| r1788_2(int) = Load[x] : &:r1788_1, ~m?
|
||||
# 1788| r1788_3(glval<int>) = VariableAddress[y] :
|
||||
# 1788| r1788_4(int) = Load[y] : &:r1788_3, ~m?
|
||||
# 1788| r1788_5(int) = Add : r1788_2, r1788_4
|
||||
# 1788| r1788_6(glval<int>) = VariableAddress[x] :
|
||||
# 1788| mu1788_7(int) = Store[x] : &:r1788_6, r1788_5
|
||||
# 1791| r1791_1(glval<int>) = VariableAddress[w] :
|
||||
# 1791| mu1791_2(int) = Uninitialized[w] : &:r1791_1
|
||||
# 1792| r1792_1(glval<int>) = VariableAddress[x] :
|
||||
# 1792| r1792_2(int) = Load[x] : &:r1792_1, ~m?
|
||||
# 1792| r1792_3(glval<int>) = VariableAddress[w] :
|
||||
# 1792| mu1792_4(int) = Store[w] : &:r1792_3, r1792_2
|
||||
# 1792| r1792_5(glval<int>) = VariableAddress[x] :
|
||||
# 1792| r1792_6(int) = Load[x] : &:r1792_5, ~m?
|
||||
# 1792| r1792_7(int) = Constant[1] :
|
||||
# 1792| r1792_8(int) = Add : r1792_6, r1792_7
|
||||
# 1792| v1792_9(void) = Switch : r1792_8
|
||||
#-----| Default -> Block 2
|
||||
|
||||
# 1793| Block 2
|
||||
# 1793| v1793_1(void) = NoOp :
|
||||
# 1794| r1794_1(glval<int>) = VariableAddress[x] :
|
||||
# 1794| r1794_2(int) = Load[x] : &:r1794_1, ~m?
|
||||
# 1794| r1794_3(glval<int>) = VariableAddress[w] :
|
||||
# 1794| r1794_4(int) = Load[w] : &:r1794_3, ~m?
|
||||
# 1794| r1794_5(int) = Add : r1794_2, r1794_4
|
||||
# 1794| r1794_6(glval<int>) = VariableAddress[x] :
|
||||
# 1794| mu1794_7(int) = Store[x] : &:r1794_6, r1794_5
|
||||
# 1797| r1797_1(glval<int>) = VariableAddress[x] :
|
||||
# 1797| r1797_2(int) = Load[x] : &:r1797_1, ~m?
|
||||
# 1797| r1797_3(glval<int>) = VariableAddress[w] :
|
||||
# 1797| mu1797_4(int) = Store[w] : &:r1797_3, r1797_2
|
||||
# 1797| r1797_5(glval<int>) = VariableAddress[w2] :
|
||||
# 1797| r1797_6(glval<int>) = VariableAddress[w] :
|
||||
# 1797| r1797_7(int) = Load[w] : &:r1797_6, ~m?
|
||||
# 1797| mu1797_8(int) = Store[w2] : &:r1797_5, r1797_7
|
||||
# 1797| r1797_9(glval<int>) = VariableAddress[w2] :
|
||||
# 1797| r1797_10(int) = Load[w2] : &:r1797_9, ~m?
|
||||
# 1797| r1797_11(int) = CopyValue : r1797_10
|
||||
# 1797| v1797_12(void) = Switch : r1797_11
|
||||
#-----| Default -> Block 3
|
||||
|
||||
# 1798| Block 3
|
||||
# 1798| v1798_1(void) = NoOp :
|
||||
# 1799| r1799_1(glval<int>) = VariableAddress[x] :
|
||||
# 1799| r1799_2(int) = Load[x] : &:r1799_1, ~m?
|
||||
# 1799| r1799_3(glval<int>) = VariableAddress[w] :
|
||||
# 1799| r1799_4(int) = Load[w] : &:r1799_3, ~m?
|
||||
# 1799| r1799_5(int) = Add : r1799_2, r1799_4
|
||||
# 1799| r1799_6(glval<int>) = VariableAddress[x] :
|
||||
# 1799| mu1799_7(int) = Store[x] : &:r1799_6, r1799_5
|
||||
# 1802| r1802_1(glval<int>) = VariableAddress[v] :
|
||||
# 1802| r1802_2(glval<int>) = VariableAddress[x] :
|
||||
# 1802| r1802_3(int) = Load[x] : &:r1802_2, ~m?
|
||||
# 1802| mu1802_4(int) = Store[v] : &:r1802_1, r1802_3
|
||||
# 1802| r1802_5(glval<int>) = VariableAddress[v2] :
|
||||
# 1802| r1802_6(glval<int>) = VariableAddress[v] :
|
||||
# 1802| r1802_7(int) = Load[v] : &:r1802_6, ~m?
|
||||
# 1802| mu1802_8(int) = Store[v2] : &:r1802_5, r1802_7
|
||||
# 1802| r1802_9(glval<int>) = VariableAddress[v2] :
|
||||
# 1802| r1802_10(int) = Load[v2] : &:r1802_9, ~m?
|
||||
# 1802| r1802_11(int) = CopyValue : r1802_10
|
||||
# 1802| v1802_12(void) = Switch : r1802_11
|
||||
#-----| Default -> Block 4
|
||||
|
||||
# 1803| Block 4
|
||||
# 1803| v1803_1(void) = NoOp :
|
||||
# 1804| r1804_1(glval<int>) = VariableAddress[x] :
|
||||
# 1804| r1804_2(int) = Load[x] : &:r1804_1, ~m?
|
||||
# 1804| r1804_3(glval<int>) = VariableAddress[v] :
|
||||
# 1804| r1804_4(int) = Load[v] : &:r1804_3, ~m?
|
||||
# 1804| r1804_5(int) = Add : r1804_2, r1804_4
|
||||
# 1804| r1804_6(glval<int>) = VariableAddress[x] :
|
||||
# 1804| mu1804_7(int) = Store[x] : &:r1804_6, r1804_5
|
||||
# 1807| r1807_1(glval<int>) = VariableAddress[z] :
|
||||
# 1807| r1807_2(glval<int>) = VariableAddress[x] :
|
||||
# 1807| r1807_3(int) = Load[x] : &:r1807_2, ~m?
|
||||
# 1807| mu1807_4(int) = Store[z] : &:r1807_1, r1807_3
|
||||
# 1808| r1808_1(glval<int>) = VariableAddress[z] :
|
||||
# 1808| r1808_2(int) = Load[z] : &:r1808_1, ~m?
|
||||
# 1808| v1808_3(void) = Switch : r1808_2
|
||||
#-----| Default -> Block 5
|
||||
|
||||
# 1809| Block 5
|
||||
# 1809| v1809_1(void) = NoOp :
|
||||
# 1810| r1810_1(glval<int>) = VariableAddress[x] :
|
||||
# 1810| r1810_2(int) = Load[x] : &:r1810_1, ~m?
|
||||
# 1810| r1810_3(glval<int>) = VariableAddress[z] :
|
||||
# 1810| r1810_4(int) = Load[z] : &:r1810_3, ~m?
|
||||
# 1810| r1810_5(int) = Add : r1810_2, r1810_4
|
||||
# 1810| r1810_6(glval<int>) = VariableAddress[x] :
|
||||
# 1810| mu1810_7(int) = Store[x] : &:r1810_6, r1810_5
|
||||
# 1813| r1813_1(glval<int>) = VariableAddress[z2] :
|
||||
# 1813| r1813_2(glval<int>) = VariableAddress[z] :
|
||||
# 1813| r1813_3(int) = Load[z] : &:r1813_2, ~m?
|
||||
# 1813| mu1813_4(int) = Store[z2] : &:r1813_1, r1813_3
|
||||
# 1813| r1813_5(glval<int>) = VariableAddress[z2] :
|
||||
# 1813| r1813_6(int) = Load[z2] : &:r1813_5, ~m?
|
||||
# 1813| r1813_7(int) = CopyValue : r1813_6
|
||||
# 1813| v1813_8(void) = Switch : r1813_7
|
||||
#-----| Default -> Block 6
|
||||
|
||||
# 1814| Block 6
|
||||
# 1814| v1814_1(void) = NoOp :
|
||||
# 1815| r1815_1(glval<int>) = VariableAddress[z2] :
|
||||
# 1815| r1815_2(int) = Load[z2] : &:r1815_1, ~m?
|
||||
# 1815| r1815_3(glval<int>) = VariableAddress[x] :
|
||||
# 1815| r1815_4(int) = Load[x] : &:r1815_3, ~m?
|
||||
# 1815| r1815_5(int) = Add : r1815_4, r1815_2
|
||||
# 1815| mu1815_6(int) = Store[x] : &:r1815_3, r1815_5
|
||||
# 1817| v1817_1(void) = NoOp :
|
||||
# 1785| v1785_6(void) = ReturnVoid :
|
||||
# 1785| v1785_7(void) = AliasedUse : ~m?
|
||||
# 1785| v1785_8(void) = ExitFunction :
|
||||
|
||||
perf-regression.cpp:
|
||||
# 6| void Big::Big()
|
||||
# 6| Block 0
|
||||
|
||||
Reference in New Issue
Block a user